Essays about: "DiMArch"

Found 5 essays containing the word DiMArch.

  1. 1. Acoarse grain reconfigurable memory architecture for linear algebra and deep neural networks

    University essay from KTH/Skolan för elektroteknik och datavetenskap (EECS)

    Author : Cyril Armand Koenig; [2022]
    Keywords : ;

    Abstract : Companies and institutions around the world have been working to develop machines with always more computing power. This race has now found its new objective: hexascale computing (with 1018 flops machines). READ MORE

  3. 2. Low Density Parity Check Encoder and Decoder on SiLago Coarse Grain Reconfigurable Architecture

    University essay from KTH/Skolan för elektroteknik och datavetenskap (EECS)

    Author : Weijiang Kong; [2019]
    Keywords : LDPC; CGRA; Reconfigurable architecture; VLSI design; ASIC; LDPC; CGRA; Konfigurerbar arkitektur; VLSI design; ASIC;

    Abstract : Low density parity check (LDPC) code is an error correction code that has been widely adopted as an optional error correcting operation in most of today’s communication protocols. Current design of ASIC or FPGA based LDPC accelerators can reach Gbit/s data rate. READ MORE

  4. 3. Development of a Massively Parallel Coarse Grained Reconfigurable Fabric verification Environment using Universal Verification Methodology

    University essay from KTH/Skolan för informations- och kommunikationsteknik (ICT)

    Author : Arun Jayabalan; [2016]
    Keywords : DRRA; DiMArch; UVM; Verification;

    Abstract : According to the International Roadmap for semiconductors (ITRS), there should be a 1000X improvement in performance with only 120% increase in the power budget and no increase in the design team size to deal with designs that are 10X more complex. One solution to cope with this complexity is to increase the granularity of the building blocks for developing new architectures. READ MORE

  5. 4. Module-level Verification For DRRA and DiMarch

    University essay from KTH/Skolan för informations- och kommunikationsteknik (ICT)

    Author : Tuna Becerik Gökmen; [2013]
    Keywords : ;

    Abstract : This thesis presents a verification process for the electronic hardware design implemented using Very-high-speed integrated circuits Hardware Description Languages (VHDL). In this study, Register Transfer Level(RTL) modules are verified. READ MORE

  6. 5. Distributed Memory Architecture with Hardware Graph Array for Configuring the Network Interconnections.

    University essay from KTH/Skolan för informations- och kommunikationsteknik (ICT)

    Author : Qiang Ge; [2012]
    Keywords : ;

    Abstract : The Network-on-chip is considered to be a promising architecture with the advent of increase in the integration of the distributed processing elements. The conflict of data transfer through the network became an urgent issue that need to be solved. READ MORE