Essays about: "HVDC using Matlab"
Found 5 essays containing the words HVDC using Matlab.
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1. Closed-loop control and data- recording of a modular-multilevel converter (MMC)
University essay from KTH/Skolan för elektroteknik och datavetenskap (EECS)Abstract : Modular multilevel converters (MMCs) are the preferred converter solution in flexible ac transmission systems (FACTS) and high-voltage direct current (HVDC) applications. This is due to the high quality of the voltage and current signals, lower overall losses, and fewer problems with switching-related EMI. READ MORE
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2. Design and performance comparison of Two-level and Multilevel Converters for HVDC Applications
University essay fromAbstract : The purpose of this thesis is to compare a two-level and a multilevel converter for HVDC substation. For this study, both topologies were designed with different modulation strategies and compared on the basis of size, power losses and impact on power quality. READ MORE
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3. Detection and location of HVDC commutation faults from PMU data
University essay from Lunds universitet/Industriell elektroteknik och automationAbstract : Commutation Failures in LCC HVDC converters is a topic that is normally addressed from the component perspective, looking at converters’ internal signals. How these commutation failures affect the outer AC network is not deeply understood yet. READ MORE
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4. Power Loss Evaluation of Submarine Cables in 500 MW Offshore Wind Farm
University essay from Uppsala universitet/Institutionen för geovetenskaperAbstract : The main objective of this thesis is to develop a new methodology to evaluate the transmission cable losses of wind-generated electricity. The research included the power loss variations of submarine cables in relation to the line length, cable capacity and the transmission technology in an offshore wind farm having a capacity of 500 MW. READ MORE
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5. High Level Synthesis of FPGA-Based Digital Filters
University essay from Uppsala universitet/Institutionen för informationsteknologiAbstract : This thesis work is aimed at the high level synthesis of FPGA based IIR digital filters using Vivado HLS produced by Xilinx and HDL coder produced by MathWorks. The Higher Layer Model of the filter was designed in Vivado HLS, MATLAB and Simulink. Simulations, verification and Synthesis of the RTL code was done for both tools. READ MORE