Essays about: "Hardware abstraction"

Showing result 1 - 5 of 43 essays containing the words Hardware abstraction.

  1. 1. Deep Learning Model Deployment for Spaceborne Reconfigurable Hardware : A flexible acceleration approach

    University essay from KTH/Skolan för elektroteknik och datavetenskap (EECS)

    Author : Javier Ferre Martin; [2023]
    Keywords : Space Situational Awareness; Deep Learning; Convolutional Neural Networks; FieldProgrammable Gate Arrays; System-On-Chip; Computer Vision; Dynamic Partial Reconfiguration; High-Level Synthesis; Rymdsituationstänksamhet; Djupinlärning; Konvolutionsnätverk; Omkonfigurerbara Field-Programmable Gate Arrays FPGAs ; System-On-Chip SoC ; Datorseende; Dynamisk partiell omkonfigurering; Högnivåsyntes.;

    Abstract : Space debris and space situational awareness (SSA) have become growing concerns for national security and the sustainability of space operations, where timely detection and tracking of space objects is critical in preventing collision events. Traditional computer-vision algorithms have been used extensively to solve detection and tracking problems in flight, but recently deep learning approaches have seen widespread adoption in non-space related applications for their high accuracy. READ MORE

  3. 2. Novel Method of ASIC interface IP development using HLS

    University essay from Lunds universitet/Institutionen för elektro- och informationsteknik

    Author : Anestis Athanasiadis; Chandranshu Mishra; [2023]
    Keywords : High Level Synthesis; HLS; Untimed C ; Control logic; I3C; clock-accurate design; IP development; Technology and Engineering;

    Abstract : High-Level Synthesis(HLS) is a design methodology that enables designers to implement hardware from high-level coding languages, such as C, C++, or System C. It provides designers with the ability to convey their design at a higher level of abstraction, which allows more emphasis on an algorithm and functional aspects of design instead on low-level hardware details. READ MORE

  4. 3. The Global Interconnection Scheme of Silago : RTL Design and Verification

    University essay from KTH/Skolan för elektroteknik och datavetenskap (EECS)

    Author : Tong Lou; [2023]
    Keywords : Silago; global interconnection; synchronous dataflow; network on chip; Silago; global sammankoppling; synkront dataflöde; nätverk på chip;

    Abstract : The Silago concept introduces a hardware-centric platform that is based on coarse-grained reconfigurable fabrics and networks on chips(NoCs). With the intra-region and inter-region NoC, the Silago platform can form resource clusters to host various applications. READ MORE

  5. 4. Modularity, Scalability, Reusability, Configurability, and Interoperability of ASIC/FPGA Verification IP

    University essay from KTH/Skolan för elektroteknik och datavetenskap (EECS)

    Author : Trupti Rao; [2022]
    Keywords : Verification Intellectual Property; UniversalVerification Methodology; Avalon Streaming Interface; Object-oriented Programming;

    Abstract : The complexity of chip design has been exponentially rising, resulting in increased complexity and costs in chip verification. This rise in complexity results in increased time to market and increases risks of chip in fabrication, that can be catastrophic and result in major losses. READ MORE

  6. 5. Acoarse grain reconfigurable memory architecture for linear algebra and deep neural networks

    University essay from KTH/Skolan för elektroteknik och datavetenskap (EECS)

    Author : Cyril Armand Koenig; [2022]
    Keywords : ;

    Abstract : Companies and institutions around the world have been working to develop machines with always more computing power. This race has now found its new objective: hexascale computing (with 1018 flops machines). READ MORE