Essays about: "On-chip memory"
Showing result 1 - 5 of 62 essays containing the words On-chip memory.
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1. Optimizing on-chip Machine Learning for Data Prefetching
University essay from Göteborgs universitet/Institutionen för data- och informationsteknikAbstract : The idea behind data prefetching is to speed up program execution by predicting what data is needed by the processor, before it is actually needed. Data prefetching is commonly performed by prefetching the next memory address in line, but there are other, more sophisticated approaches such as machine learning. READ MORE
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2. Low-power Acceleration of Convolutional Neural Networks using Near Memory Computing on a RISC-V SoC
University essay from Lunds universitet/Institutionen för elektro- och informationsteknikAbstract : The recent peak in interest for artificial intelligence, partly fueled by language models such as ChatGPT, is pushing the demand for machine learning and data processing in everyday applications, such as self-driving cars, where low latency is crucial and typically achieved through edge computing. The vast amount of data processing required intensifies the existing performance bottleneck of the data movement. READ MORE
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3. Design and evaluation of architectures for efficient generation of control sequences
University essay from Lunds universitet/Institutionen för elektro- och informationsteknikAbstract : Ultra millimeter-wave (mmWave) radars have become a vital sensor in automotive, surveillance, and consumer electronics thanks to its precise measurements and low power consumption. However, they required a precise control to coordinate their different modules and produce meaningful data. READ MORE
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4. Investigating Machine Learning for verification of AMBA APB protocol.
University essay from Lunds universitet/Institutionen för elektro- och informationsteknikAbstract : It is a well-known fact that in any Application Specific Integrated Circuit (ASIC) design, verification consumes most time and resources. And when it comes to huge designs, finding bugs can be tedious given the area and the complexity. As per Moore’s law, the design complexity is increasing exponentially due to the growing demand for performance. READ MORE
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5. AXI-PACK : Near-memory Bus Packing for Bandwidth-Efficient Irregular Workloads
University essay from KTH/Skolan för elektroteknik och datavetenskap (EECS)Abstract : General propose processor (GPP) are demanded high performance in dataintensive applications, such as deep learning, high performance computation (HPC), where algorithm kernels like GEMM (general matrix-matrix multiply) and SPMV (sparse matrix-vector multiply) kernels are intensively used. The performance of these data-intensive applications are bounded with memory bandwidth, which is limited by computing & memory access coupling and memory wall effect. READ MORE
