Essays about: "cmos power amplifier design"
Showing result 1 - 5 of 28 essays containing the words cmos power amplifier design.
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1. Current-Mode Class D Power Amplifier for 2.4GHz Wi-Fi
University essay from KTH/Skolan för elektroteknik och datavetenskap (EECS)Abstract : Modern wireless communication techniques employed in the Wi-Fi® protocol, such as orthogonal frequency-division multiplexing exhibit analogue signals with high peak-to-average power ratio. Therefore, power amplifiers for Wi-Fi suffer from low efficiency when operating in back-off mode, away from their maximum efficiency at peak power. READ MORE
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2. Configurable, scalable single-ended sense amplifier with additional auxiliary blocks for low-power two-port memories in advanced FinFET technologies
University essay from Lunds universitet/Institutionen för elektro- och informationsteknikAbstract : System on Chip (SoC) designs contain a variety of Intellectual Property (IP) cores, including digital signal processing blocks, media and graphics processing units, as well as processing core units that employ multiple-port memories to enhance performance and bandwidth. These memories allow parallel read/write operations from the same memory blocks from different ports. READ MORE
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3. Hybrid Coupler for LMBA Input Match Using an Active Inductor
University essay from Linköpings universitet/Elektroniska Kretsar och SystemAbstract : With the increase in demand for compact and high data rate communication systems, there is a need for high efficiency with modulated signals (PAPR 5-10 dB) for base-station power amplifiers. One of the famous architectures used to achieve this is Doherty architecture. READ MORE
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4. A design of a 100 MS/s, 8-bit Pipelined ADC in CMOS
University essay from Lunds universitet/Institutionen för elektro- och informationsteknikAbstract : The thesis focuses on designing and simulating an 8-bit high-speed fully differential pipelined Analog to Digital Converter (ADC) in the 65nm Complementary Metal-Oxide-Semiconductor (CMOS) technology by using the software Cadence Virtuoso. The aim is to increase the operation speed of the ADC for communication systems without reducing the performance, in the meantime, the low power consumption and the low complexity should also be required when considering future implementation. READ MORE
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5. Power Supply Rejection (PSR) Enhancement Techniques for Fully Integrated Low-Dropout (LDO) Regulators
University essay from Linköpings universitet/Elektroniska Kretsar och SystemAbstract : In this present world, there is a huge requirement of portable devices for that the analysis of low-dropout or LDO regulators have been on high priority. So, for every respective device, there is a power budget that acts as the main constraint to design an LDO. The LDO design aims to suppress the noise and supply noise-free or low noise output. READ MORE