Design and Implementation of Common Drain Class-B RF Power Amplifier in 90 nm CMOS Technology

Abstract: Power Amplifer (PA), is a key component in a wireless communication system. It is challanging to design a PA having sucient gain, linearity and eciency all at the same time. Linearity is important to avoid interference among the channels while high effciency corresponds to longer battery life. Gain is important to reduce multiple stages. All the RF power ampli ers are made in common source configuration which offers high power gain but significant nonlinearity. To improve linearity, the amplifer is operated in backoff or advanced techniques like digital predistortion are used. On the other hand, common drain amplifer has inherent potential to provide both linearity and efficiency. Operating the common drain in class B mode can provide high efficiency as well as additional linearity due to suppression of nonlinear gate-source capacitance. The scope of this thesis is to design a stable single-ended as well as dierential common drain class-B RF power ampli er, while maintaining adequate transducer gain so that the power added efficiency (PAE) is not compromised by low gain and thus resulting in better overall performance. The technology to be employed for the implementation of the amplifer is the 90 nm CMOS process and the operating frequency is 2.55 GHz, the 3GPP Long Term Evolution (LTE) standard. For additional performance evaluation, the results are to be compared with that of a single-ended common source amplifer.