CRASIC: Customisation of Coarse Grain Recon gurable Architectures

Abstract: The gap between CGRAs and ASIC designs is a major issue for all digital designers. The main objective of the following thesis is developing a method to customize the design according to the application to increase performance and decrease the area of the chip. although there are commercial high level synthesis tools which are able to synthesis an algorithmic level description of an application to ASIC, how ever they are not able to generate recon gurable hardware operating as multi-mode ASIC. In this project a tool has been developed which sweeps the design space between the fully recon gurable CGRA hardware template and ASIC. this tool generates a customized hardware based on the implemented applications and user speci cations by eliminating unused/unwanted components of the design. FFT and CP algorithms are used in this research in order to have some solid results for area and power consumption of the customized design. The results shows up to 44 percent reduction in area of a fabric containing both CP and 2048 points FFT and 20 percent reduction in power consumption for 2048 Point FFT on the very same fabric. Developing this approach on CGRAs can enable designers to have their ASIC designs just by implementing an algorithm on the fabric and then receive a customized fabric close to ASIC with some small automatic steps.