Hardware design and implementation of the Schmidl-Cox synchronization algorithm for an OFDM transceiver

Abstract: The subject of this document is the VHDL firmware implementation of a coarse synchronization method for a 4G/5G transceiver. The method of choice is the Schmidl-Cox synchronization algorithm that is applied to the OFDM transmission standard as preparation for later conversion to the FBMC method. This algorithm is first developed and validated in a MATLAB floating point environment. After this a thorough analysis step is conducted to devise a fixed point implementation of negligible perfor- mance loss. Thereafter a main contribution of this work comes through the proposal of a low-complexity hardware architecture that efficiently implements this fixed point Schmidl-Cox algorithm. This architecture is described in VHDL and validated through extensive simulations after integration with the transceiver model. Simulation results and logic syn- thesis targeting a Zynq 7020 FPGA board illustrate the efficiency of the proposed implementation.