A Comparative Study of Efficient Power Amplifiers in CMOS

Abstract: During later years communication schemes for handheld devices have increased in complexity due to the desire to increase the throughput, i.e. the amount of information sent over a medium simultaneously. Increasing throughput can be accomplished, not only by modulating the phase or frequency, but also the amplitude. This leads to tougher requirements on the power amplifier. The conventional power amplifiers, which have the ability to follow the envelope of the carrier, are inefficient. This thesis aims to compare two old but revived architectures which exploit high-efficiency amplifiers and still have a linear relationship between the input and output. The architectures; the Polar Linearization Technique and Outphasing share the same foundation. Based on literature, the polar technique have been more successful of employing examples fufilling communication standards. The polar technique is also more versatile regarding power combiners, distortion correction and alternative implementations. The simulations performed in this thesis results show that the polar amplifier is less sensitive to process variations and has higher maximum efficiency. On the other hand, the outphasing topology have the highest linearity figures.