Design of a VCO based ADC in a 180 nm CMOS process for use in
positron emission tomography

Abstract: A Voltage-Controlled Oscillator (VCO)-based Analog-to-Digital Converter (ADC)
for use in Positron Emission Tomography has been designed in a 180 nm CMOS
process. The VCO-based ADC is a time-based architecture with a first-order
noise shaping ability. The ADC designed in this thesis utilizes a
five-element current-starved VCO-core and a new counter architecture. The
work deals with the theory and limitations for designing and evaluate these
ADC architectures. The ADC sampling frequency is set to 50 MHz with an input
signal bandwidth of 500 kHz. Thus, an oversampling ratio (OSR) of 50. The ADC
achieves a peak Signal-to-Noise Ratio (SNR) of 88 dB or approximately 14.3
bit while dissipating only 1.18 mW from a 1.8 V supply and occupying an
active chip-area of <0.01 mm^2.

the work was carried out at the fraunhofer - institut für integrierte
schaltungen (iis), in erlangen, germany under a time period of approximately
five months. a part of the thesis was also to take part in the patent
application process for a new counter architecture, described in this thesis.