Virtual environment for assembler code analysis

Abstract: The hardware that computers consist of may for dierent reasons be dicult to monitor, the price may be high or the hardware itself may be unavailable. The most apparent reason though is the fact that hardware generally is not transparent, i.e. the hardware does not provide informa- tion on how a task is conducted, only its result. To provide a virtual en- vironment that enables simulation according to specic input parameters eectively solves many of the issues associated with hardware evaluation. Simulation has applications everywhere, not the least in computer science: From the low level of micro code all the way up to interpreting a high level implementation on top of a profound software stack. This thesis entails a virtual environment running a MIPS pipeline, although the simulator is implemented in the high level language C, it executes simulation at the fairly low level of assembler code. When provided with a user specied conguration le, the environment allows simulation of MIPS assembler programs, through the CPU, via interconnecting buses, ending at the level of virtual memory.