Simulated molecular adder circuits on a surface of DNA : Studying the scalability of surface chemical reaction network digital logic circuits

University essay from KTH/Skolan för elektroteknik och datavetenskap (EECS)

Abstract: The behavior of the Deoxyribonucleic Acid (DNA) molecule can be exploited to perform useful computation. It can also be ”programmed” using the language of Chemical Reaction Networks (CRNs). One specialized CRN construct is the Surface Chemical Reaction Network (SCRN). The SCRN construct can implement asynchronous cellular automata, which can in turn be used to implement digital logic circuits. SCRN based digital logic circuits are thought to have several advantages over regular CRN circuits. One of these proposed advantages is their scalability. This thesis investigates the scalability of SCRN based adder circuits, how does an increase in the number of bits affect the time required for the circuit to produce a correct result? Additionally, how is the throughput of the circuit affected when multiple additions are performed in a pipelined fashion? These questions are studied through experiments where the execution of optimized SCRN adder circuits is simulated. Due to the stochastic nature of SCRNs each such execution is all but guaranteed to be unique, requiring the simulation of the circuits to be repeated until a sufficiently large statistical sample has been collected. The results show these samples to follow a Gaussian distribution, regardless of the number of bits or the number of pipelined operations. The experiments show the simulated latency of the studied SCRN adder circuits to scale linearly with the number of input bits. The results also show that the throughput can be greatly improved through the pipelining of multiple operations. However, the results are inconclusive as to the maximum possible throughput of SCRN adder circuits. A conclusion of the project is that SCRN digital logic circuit design could conceivably benefit from the implementation of specialized components beyond the standard logic gates.

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