Performance evaluation and analysis of Barrelfish using Simics
Abstract: Personal computing hardware is becoming ever more complex with more cores being added. It is moving from being a multi-core to a many-core system. In the next ten years we are expected to see hundreds of cores on one single chip. It is also very likely we will see more specialized hardware in coexistence with general purpose processing units. The cache-coherent shared-memory operating systems of today do not scale well on the hardware of tomorrow. As the number of cores grows, so does the complexity of the interconnects. The hardware cache-coherence protocols shared-memory operating systems of today rely upon subsequently become increasingly expensive with a greater overhead. As a result, it is entirely possible that operating system of tomorrow will have to handle non-coherent memory. The expected increase in hardware diversity and issues such as cache coherency on hundred core systems poses new challenges for operating system designers. Barrelfish is a research operating system with the purpose of exploring operating-system design of the future. It is a multi-kernel operating system for multi-core systems and utilizes message passing as a way of communication between kernels. Barrelfish assumes no shared-memory, however it does not explicitly forbid shared-memory. The purpose of this thesis is to performance evaluate Barrelfish using Simics with a modeled approximation of an existing cache structure from a modern processor. A Wool ported version of the Barcelona OpenMP Task suite was used for the purpose of work load simulation, and a comparison between Linux and Barrelfish has been made.
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