DMA processor
Abstract: The DMA (Direct Memory Access) controller, is often a non-programmable
hardware. As new peripheral interfaces are introduced there is often a need
to change the DMA operation and therefore the design of the DMA controller.
Changing the design of the DMA controller is often expensive and
time-consuming. Instead, a fully programmable DMA processor can alter the
behaviour by simply changing a control program.
This paper describes an approach for a programmable DMA processor for a
future ETRAX processor developed by Axis Communications. To reach the design
solution, different instruction set architectures were simulated and
investigated. The result is a fully programmable DMA processor with one RISC
core and several burst controllers that handles the data transfers. It can
transfer data in parallel with up to 16 channels. The DMA processor is able
to work with 1 Gbit/s full duplex Ethernet when the DMA processor is running
at 100 MHz. The program that controls the DMA operations is stored in a
local instruction memory of the DMA processor. When synthesized with 0.25 um
technology, the DMA controller has a 160 000 gate foot print without the
instruction memory.
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