Modeling and Characterization of an All-Digital Phase-Locked Loop

Abstract: The thesis "Modeling and Characterization of an All-Digital PLL" aims to create a behavioral model of an All-Digital Phase-Locked-Loop (ADPLL). The model should be able to perform accurate and time-effective simulations. Based on the model, a sub-block requirement will be presented as decision basis for test chip manufacturing. The wireless communications industry has grown tremendously in the recent years, leading to strong demand for smaller, faster, better and less power consuming circuits. Digital circuits have better properties in these aspects, which have resulted in great interest for more digitally intensive circuits. Since frequency synthesis is an essential part of any wireless system an all digital PLL is very attractive. Traditional simulation tools are unable to simulate a complex system like an ADPLL. Since production costs are high and it is necessary to verify the integrity of the design and the circuit behavior before first prototype, an alternative solution is needed. One solution is to use an event-driven simulation technique that only focus on the events that occur at each clock flank. The difficulty lies in creating a realistic model of behavior. The project has focused on meeting the phase noise requirements imposed on a WCDMA / HSDPA application. The event-driven model is implemented in Matlab because of its high flexibility during development, and large variety of analytical tools. The proposed model is based on a previously published model that has been evolved in ways that were interesting for the project. The model’s construction and accuracy have been verified against the appropriate theory. By constructing a comprehensible user interface around the model, it is convenient to examine how different parameters affect system performance. The simulation results of the model establish how the different parameters affect the phase noise spectrum of the ADPLL. The TDC architecture has big influence on the phase noise and it is of big importance to use high precision in the entire system to prevent an increased in-band noise level. A time-effective simulation tool has successfully been constructed and a sub-block requirement specification has been presented.