HDL Implementation of CCSDS Standards

University essay from Luleå/Department of Computer Science, Electrical and Space Engineering

Author: Jonatan Brodin; [2013]

Keywords: Verilog; FPGA; CCSDS; HDL; ECSS;

Abstract: Communication to and from a satellite is a complicated endeavour. The purpose of this master thesis is to design a communications system for small satellites that will run in a Field Programmable Gate Array for use on satellites. The communication system is developed in preparation for new standards and recommendations from the European Cooperation for Space Standardization that will take into account new communications protocols from the Consultative Committee for Space Data Systems. The existing standards and recommendations that describe the current version of protocols were thoroughly studied. The communication system’s design is based on the information gleaned for these documents, such as the structure of frames and packets.

The hardware for the communication system is designed in the hardware description language Verilog. This code is intended to be loaded into a Field Programmable Gate Array. The communication system is required to be able to receive and decode telecommands and extract packets out of the telecommand frames. The commands in these packets should be either executed or sent on to the connected CPU. The system should also be able to construct packets from data sent from the CPU, place the packets in frames, encode the frames and send them as telemetry. The code is simulated using a multitude of test messages and the results were reviewed. Finally synthesis of the code is done to see if it can function in the Field Programmable Gate Array.

The final communication system design fulfils all the demands set by the standards and recommendations. The system can detect all the errors that it is designed to detect and the design fits nicely inside the Microsemi ProASIC3E A3PE3000 Field Programmable Gate Array.

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