Implementation of an SDR in Verilog

Abstract: This report presents an implementation of the software part in a software definedradio. The radio is not entirely implemented in software and therefore there arecertain limitations on the received signal. The parts implemented are oscillator,decimation filter, carrier synchronization, time synchronization, package detection,and demodulation. Different algorithms were tested for the different partsto measure the power consumption. To understand how the number of bits usedto represent the signal affects the power consumption, the number of bits wasreduced from 20 bits to 10 bits. This reduction reduced the power consumptionfrom 2.57mW to 1.89mW. A small change in the choice of algorithms was thenmade which reduced the power consumption to 1.86mW. Then the clock rate wasreduced for some parts of the system which reduced the power consumption to1.05mW.