Hardware-in-The-Loop Simulation of a High Speed Servo System

University essay from KTH/Maskinkonstruktion (Inst.)

Author: Eiður Ágústsson; [2013]

Keywords: ;

Abstract: In production industries there is a constant demand for shorter time to market and lower development costs. Using models and simulations has been shown to decrease development time and increase product quality. One reason for this is that these methods allow development and testing of control systems before actual prototypes are available. The purpose of this thesis is to implement a Hardware-in-the-loop simulation of the MY500 solder jet printer, which is produced by Micronic Mydata AB. The MY500 has high accuracy and speed requirements, resulting in a short control loop, which puts hard constraints on the model calculation time. The simulation is implemented on a dSPACEMicroAutoBox, using the MATLAB toolboxes Simulink and SimMechanics. It communicates with the control system via SPI and implements an existing SimMechanics model and a newly developed Simulink model. The Simulink model developed in this thesis was found to be a sufficiently realistic simplification of the SimMechanics model. Furthermore, the findings show that the Sim-Mechanics model cannot be run in closed loop on the chosen hardware due to its extensive complexity. The thesis also shows that when using the internal clock, even the shortest model step time allowed by the hardware is not sufficient to perform a stable HIL simulation. Lastly, the SPI implementation tested in this thesis introduced computational delays into the control loop of the MY500, which led to the system only being able to calculate one axis. This thesis concludes that even though the current implementation has some limitations, there is reason to continue the work and making a good simulator of the MY500. Two main avenues of investigation are; firstly, implementing an external interrupt for the HIL simulation, which should allow a larger time step and eliminate jitter in the model output. Secondly, moving the SPI communication code out of the control loop and instead implementing it directly on the FPGA, which should minimize the computational delay added by SPI and thereby allows control of more than one axis.

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