Design of a DVB-T Receiver : For SFN on a DSP-Processor

Abstract: The goal of this thesis was to implement a DVB-T receiver on Coresonic’s DSP-processor and attempt to evaluate how to design a receiver that is robust against very strong echoes with a long delay. Long delayed echoes is very common in Single Frequency Networks (SFN) which is why focus was put on finding algorithms that work well in SFN.The thesis involved analyzing different algorithms involved in making a DVB-T receiver where the focus was to find a good channel estimation algorithm. The thesis also included programming the DSP-processor and making some smaller modifications to their hardware solution to integrate their error correction hardware. After finding relevant articles with promising algorithms a small transmitter, channel and receiver was modeled in Matlab in order to try the different algorithms. After testing the different algorithms some of the simpler ones were first implemented to quickly get a working receiver. The implementation was however time consuming and all of the most appropriate algorithms to better avert the effects of long and strong echoes where not implemented. This means some algorithms where only analyzed and discussed.The receiver performance is tested and simulated in Coresonic’s DSP simulator. The receiver does not fully meet the requirements set by NorDig when it comes to handling long delay spread echoes with a magnitude of 0db when tested in the DSP processor simulator. The receiver is however able to handle the Ricean channel at a SNR of 19 Db and Rayleigh channel at an SNR of 24 Db.This report is the result of the final thesis of a Master of Science in Computer Engineering at Linköpings Tekniska Högskola. The thesis was performed at Coresonic AB in Mjärdevi Linköping.