Low-power Microprocessor based on Stack-Architecture

Abstract: There are many applications of microprocessors in embedded applications, where power efficiency becomes a critical requirement, e.g. wearable or mobile devices in healthcare, space instrumentation and handheld devices. One of the methods of achieving low power operation is by simplifying the device architecture. RISC/CISC processors consume considerable power because of their complexity, which is due to their multiplexer system connecting the register file to the functional units and their instruction pipeline system. On the other hand, the Stack machines are comparatively less complex due to their implied addressing to the top two registers of the stack and smaller operation codes. This makes the instruction and the address decoder circuit simple by eliminating the multiplexer switches for read and write ports of the register file. They are also optimized for procedure calls because they operate on stack instead of register, which reduces the memory size. All these factors make a stack machine power-efficient. In this thesis project a Stack-based processor was designed in 65 nm CMOS technology. The area of the processor was 0.16 sq.mm, which is very compact. The processor consumed about 20 uW/MHz when powered by a 0.6 V supply and 85 uW/MHz at 1.2 V. This is remarkably less than typical 250 to 450 uW/MHz consumed by the commercial grade low-power microcontrollers. This device was tested up to a speed of 50 MHz at 1.2 V and 20 MHz at 0.6 V.