Implementation of the DSP chain of MPD radar using FPGAs and Residue Number System (RNS) Arithmetic

Abstract: With the ever increasing demands for computational power in the digital processing systems of the present and the future, the emphasis on the power consumption and the area requirements of designs is tangible. To meet these stringent requirements this paper investigates the effects of using an alternative numbering system known as the Residue Number System or RNS.

The Medium pulse repetition frequency Pulsed Doppler (MPD) radar principles are studied and the various components in the MPD DSP chain are introduced. These include filters, FFT processors, and target detectors.

The MPD signal processing chain is modeled in both binary and RNS number systems and their respective performance is juxtaposed. To verify the operation of the developed models, a MATLAB model of the DSP system is also provided.

To describe the DSP system in hardware VHDL is used as the hardware description language of choice. Verification of the correct operation of the design using simulation is carried out using Mentor Graphics ModelSim software. FPGA platform is selected for implementation of the DSP system in hardware and the Xilinx ISE software is used for synthesis and placement and routing. In addition to verification through simulation the system is verified in-circuit.

The system described in VHDL is modular and divided into a number of functional, memory (RAM and ROM), and control modules. These modules are written to be synthesis friendly and the targeted systems' guidelines were followed.