Design of Highly Linear Sampling Switches for CMOS Track-and-Hold Circuits

Abstract: This thesis discusses non-linearities associated with a sampling switch and compares transmission gate, bootstrapping and bulk-effect compensation architectures at circuit level from linearity point of view for 0.35 um CMOS process. All switch architectures have been discussed and designed with an additional constraint of switch reliability. Results indicate that for a specified supply of 3.3 Volts, bulk-effect compensation does not improve third-order harmonic distortion significantly which defines the upper most limit on linearity for a differential topology. However, for low-voltage operations bulk-effect compensation improves third-order harmonic noticeably.