Impact of Pin Orientation on Routing Regularity of HPM Architectures

Abstract: In the context of regular arithmetic circuits, the effect of pin placement on the quality oflayout and routing is not well understood. Current methodologies depend on library-basedflows to design such circuits. However, the benefits of regularity are lost in the process ofautomated place and route techniques employed by these methodologies. As process technologiesgrow smaller, this will have a large effect on the yield and variability. Enforcingregularity to combat variability is being advocated in the form of restricted design rules.This thesis attempts to develop a methodology to implement customized pin orientationsfor the cells. These cells are used in the design to harness the benefits of regularity and inthe process, mitigate variability. HPM multiplier is taken as a case study and different pinorientations are tried out for the cells constituting rectangular PPRT of the multiplier.

The tool-set to be used for this project include Cadence Virtuoso for implementing the standardcell layouts, Cadence Encounter Library Characterizer to perform characterization ofthe implemented layouts and Cadence SoC Encounter to implement the HPM multiplierusing the customized standard cells.