TAM Design for Parallel Testing under Bus Bandwidth Limit

Abstract: The complexity of electronic system is increasing rapidly and many of the electronic systems   are   embedded   systems   implemented   as   system-on-chip   (SoC).   This increasing  complexity  of  SoC  leads  to  longer  test  application  time  (TAT).  One approach  to  reduce  the  TAT  is  to  perform  tests  to  several  cores  in  parallel,  which requests transporting test data in parallel instead of sequentially. In IEEE Std. 1500, it supports parallel test mode by incorporating a user-defined, parallel   test   access   mechanism   (TAM)   to   speed   up   the   testing   process.   The user-defined  TAM  means  the  detail  of  TAM  design  is  excluded  from  standard  and decided by system integrator. Therefore, we propose a customized TAM structure and two approaches to guarantee full-spatial-parallelism under a bus width limit, and aim to  minimize  the  total  number  of  wire  connections.  In  order  to  know  how  close  to optimal  solution  our  solutions  are,  we  implement  a  Simulated  Annealing  (SA) algorithm to do the comparison. The  experimental  results  of  the  two  proposed  approaches  based  on  benchmark ISCAS’89  and  ITC’02  show  the  parallelism  can  be  guaranteed  by  our  approaches while using only a few wire connections per pin, and the execution times of them are shorter compared with the SA algorithm.