FPGA prototyping of the MSP430F5172

Abstract: The aim of this master thesis is to develop a working FPGA prototypeof the MSP430F5172. This report deals with the standard stepsof FPGA recoding. It relates the implementation results to the FPGAlogic primitives and an introduction to such logic primitives is providedwhen such a discussion is presented. So the result and the theory areinterconnected throughout the content of the report. It also presents adiscussion on the extensive spectrum of tools involved in the FPGA implementationprocess from EDIF netlist generation to the final bitstreamgeneration as well as analysis tools like timing analyzer. An overview ofthe principles involved in the implementation process provides a betterunderstanding of the operation of the tools. In addition many features ofthe tools explored during the execution of the thesis is documented thatenables the reader to reduce the learning curve involved in implementingsuch a project in the future.

The device utilisation for the MSP430F5172 prototype on the Virtex5LX110 was about 25%. In spite of such a moderate device utilisationthe runtimes were as high as 3 hours which can give an idea of the complexitiesinvolved in the RTL code of modern microprocessors. Issuesfaced in the course of the thesis are also presented and discussed. Proceduresand principles that can help overcome this issues are also presented.

Finally, the FPGA prototype is subjected to basic functional tests. Theresults and code example is also provided.