On SIMD code generation for the CELL SPE processor

Abstract: This thesis project will attempt to answer the question if it is possible to gain performance by using SIMD instructions when generating code for scalar computation. The current trend in processor architecture is to equip the processors with multi-way SIMD units to form so-called throughput cores. This project uses the CELL SPE processor for a concrete implementation. To get good code quality the thesis project continues work on the code generator by Mattias Eriksson and Andrzej Bednarski based on integer linear programming. The code generator is extended to handle generation of SIMD code for 32bit operands. The result show for some basic blocks, positive impact in execution time of the generated schedule. However, further work has to be done to get a feasable run time of the code generator.