Frame rate limiter for export restricted cameras

Abstract: This master thesis describes the design of a low power and low noise CMOS circuit capable of limiting 9 frames per second. This is a part of a larger ongoing project for development and design of a low-cost IR night-vision network camera. This circuit is implemented in 0.35μm process. An RC-oscillator with voltage averaging feedback concept is used as timing reference which is capable of overcoming ± 20% of frequency variations. The circuit consumes 85 μW power when enabled and 1.853 μW power when disabled. This circuit design allows 9 frames per second. The variation in frequency due to a temperature range of -40°C to 100°C is within ±2.5% and for voltage range of 3.2V to 3.6V is within ±1%.