Essays about: "8 bit Pipelined ADC design"
Found 4 essays containing the words 8 bit Pipelined ADC design.
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1. A design of a 100 MS/s, 8-bit Pipelined ADC in CMOS
University essay from Lunds universitet/Institutionen för elektro- och informationsteknikAbstract : The thesis focuses on designing and simulating an 8-bit high-speed fully differential pipelined Analog to Digital Converter (ADC) in the 65nm Complementary Metal-Oxide-Semiconductor (CMOS) technology by using the software Cadence Virtuoso. The aim is to increase the operation speed of the ADC for communication systems without reducing the performance, in the meantime, the low power consumption and the low complexity should also be required when considering future implementation. READ MORE
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2. Implementation of a 200 MSps 12-bit SAR ADC
University essay from Lunds universitet/Institutionen för elektro- och informationsteknikAbstract : Analog-to-digital converters (ADCs) with high conversion frequency, often based on pipelined architectures, are used for measuring instruments, wireless communication and video applications. Successive approximation register (SAR) converters offer a compact and power efficient alternative but the conversion speed is typically designed for lower frequencies. READ MORE
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3. DIGITAL GAIN ERROR CORRECTION TECHNIQUE FOR 8-BIT PIPELINE ADC
University essay from Elektroniska komponenterAbstract : An analog-to-digital converter (ADC) is a link between the analog and digital domains and plays a vital role in modern mixed signal processing systems. There are several architectures, for example flash ADCs, pipeline ADCs, sigma delta ADCs,successive approximation (SAR) ADCs and time interleaved ADCs. READ MORE
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4. Low-power 8-bit Pipelined ADC with current mode Multiplying Digital-to-Analog Converter (MDAC)
University essay from Institutionen för systemteknikAbstract : In order to convert the analog information in the digital domain, pipelined analog-to-digital converter (ADC) offers an optimum balance of resolution, speed, power consumption, size and design effort. In this thesis work we design and optimize a 8-bit pipelined ADC for low-power. The ADC has stage resolution of 1. READ MORE
