Essays about: "ASIC"
Showing result 21 - 25 of 108 essays containing the word ASIC.
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21. High-Performance Beamforming for Radar Technology : A Comparative Study of GPU Beamforming Algorithms
University essay from KTH/Skolan för elektroteknik och datavetenskap (EECS)Abstract : Radar technology is widely used in today´s society, whether it is the localisation and identification of aircraft in air traffic control systems, ships in harbour management systems, or the weather forecast presented on the news. In military applications, such as in fighter jets or missile lock-on systems, the speed at which the radar processes incoming data is essential to ensure a successful outcome. READ MORE
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22. AXI-PACK : Near-memory Bus Packing for Bandwidth-Efficient Irregular Workloads
University essay from KTH/Skolan för elektroteknik och datavetenskap (EECS)Abstract : General propose processor (GPP) are demanded high performance in dataintensive applications, such as deep learning, high performance computation (HPC), where algorithm kernels like GEMM (general matrix-matrix multiply) and SPMV (sparse matrix-vector multiply) kernels are intensively used. The performance of these data-intensive applications are bounded with memory bandwidth, which is limited by computing & memory access coupling and memory wall effect. READ MORE
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23. Mapping quantized convolutional layers on the SiLago platform
University essay from KTH/Skolan för elektroteknik och datavetenskap (EECS)Abstract : Convolutional neural networks (CNNs) have been utilized in various applications, such as image classification, computer vision, etc. With development, the complexity and computation of CNNs also increase, which requires more memory and resources when deployed on devices, especially embedded systems. READ MORE
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24. Design space exploration using HLS in relation to code structuring
University essay from KTH/Skolan för elektroteknik och datavetenskap (EECS)Abstract : High Level Synthesis (HLS) is a methodology to translate a model developed in a high abstraction layer, e.g. C/C++/SystemC, that describes the algorithm into a Register-Transfer level (RTL) description like Verilog or VHDL. READ MORE
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25. Validation of efficiency of formal verification methodology for verification closure
University essay from KTH/Skolan för elektroteknik och datavetenskap (EECS)Abstract : Application Specific Integrated Circuits (ASIC) and Field Programmable Gate Arrays (FPGA) verification is quite a time consuming phase in design flow cycle and it can be done using methodologies such as Universal Verification Methodology (UVM) and formal verification.The UVM methodology is simulation based verification where in the verifier will have to trigger the Design Under Test (DUT) manually by writing sequences which target different features of the DUT and the verification environment can also have verification directives such as assertions to spot design bugs. READ MORE
