Essays about: "All Digital PLL"

Showing result 1 - 5 of 10 essays containing the words All Digital PLL.

  1. 1. System Level Modeling and Verification of All-digital Phase-locked Loop

    University essay from KTH/Skolan för informations- och kommunikationsteknik (ICT)

    Author : Chi Zhang; [2015]
    Keywords : ;

    Abstract : In wirelesscommunication systems, a local oscillator (LO) aims at demodulating radio-frequency signals into baseband signals. The performance of these signals determines the quality of communications which is highly affected by the phase accuracy of local oscillators. READ MORE

  2. 2. Design and Simulation of Miscellaneous Blocks of an All-Digital PLL for the 60 GHz Band

    University essay from Linköpings universitet/Linköpings universitet/ElektroniksystemTekniska högskolan; Linköpings universitet/Linköpings universitet/ElektroniksystemTekniska högskolan

    Author : Hadiyah Butt; Manjularani Padala; [2013]
    Keywords : ADPLL; PLL; DCO; TDC;

    Abstract : A phase-locked loop commonly known as PLL is widely used in communication systems. A PLL is used in radio, telecommunications, modulation and demodulation. It can be used for clock generation, clock recovery from data signals, clock distribution and as a frequency synthesizer.Most electronic circuits encounter the problem of the clock skew. READ MORE

  3. 3. Design of a Time-to-Digital Converter for an All-Digital Phase Locked Loop for the 2-GHz Band

    University essay from Linköpings universitet/Linköpings universitet/ElektroniksystemTekniska högskolan; Linköpings universitet/Linköpings universitet/ElektroniksystemTekniska högskolan

    Author : Naveen Wali; Balamurali Radhakrishnan; [2013]
    Keywords : ADPLL; TDC; DPLL; PLL;

    Abstract : An all-digital phase locked loop for WiGig systems was implemented. The developedall-digital phase locked loop has a targeted frequency range of 2.1-GHz to2.5-GHz. READ MORE

  4. 4. Design of a DCO for an All Digital PLL for the 60 GHz Band : Design of a DCO for an All Digital PLL for the 60 GHz Band

    University essay from Linköpings universitet/Linköpings universitet/ElektroniksystemTekniska högskolan; Linköpings universitet/Linköpings universitet/ElektroniksystemTekniska högskolan

    Author : Manikandan Balasubramanian; Saravana Prabhu Vijayanathan; [2013]
    Keywords : DCO; 65 nm; Oscillator; Varactor; Jitter; Differential to single; All-digital PLL; PLL;

    Abstract : The work was based on digitally controlled oscillator for an all-digital PLL in 65nm process. Phase locked loop’s were used in most of the application for clock generation and recovery as well. As the technology grows faster in the existinggeneration, there has to be quick development with the technique. READ MORE

  5. 5. A Self-compensated, Bandwidth Tracking Semi-digital PLL Design in 65nm CMOS Technol-ogy

    University essay from Linköpings universitet/ElektroniksystemLinköpings universitet/Tekniska högskolan

    Author : Mitesh Yogesh; [2012]
    Keywords : PLL; semi-digital; Bandwidth tracking; Adaptive bandwidth; Compensation; PVT; Self-Bias; charge-pump; VCO; 65nm;

    Abstract : In a conventional charge-pump based PLL design, the loop parameters such as the band-width, jitter performance, charge-pump current, pull-in range among others govern the ar-chitecture and implementation details of the PLL. Different loop parameter specificationschange with a change in the reference frequency and inmost cases, requires careful re-designof some of the PLL blocks. READ MORE