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  1. 1. Statistical Approach for the Design of Refresh-Free eDRAM with Retention Timing Constraint

    University essay from Lunds universitet/Institutionen för elektro- och informationsteknik

    Author : Arturo Prieto; [2019]
    Keywords : Memory; eDRAM; DRAM; SRAM; IC; Refresh; Statistics; Importance Sampling; Monte Carlo; Technology and Engineering;

    Abstract : In digital integrated circuits, memories are often a limiter for main performance, power and area. Over the past decade, integrated memories have gained dominance in terms of area and power cost. In applications like machine learning or image processing the area share can be above 80% consuming more than 50% of the total power budget. READ MORE