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Showing result 1 - 5 of 13 essays matching the above criteria.

  1. 1. Optimizing the instruction scheduler of high-level synthesis tool

    University essay from KTH/Skolan för elektroteknik och datavetenskap (EECS)

    Author : Zihao Xu; [2023]
    Keywords : Instruction scheduling; Scheduling algorithm; CGRA; High-level Sythnesis; SiLago; Algorithm-level Synthesis; Constraint programming; Instruktion schemaläggning; schemaläggning algoritm; CGRA; High-level Sythnesis; SiLago; Algoritm-nivå Synthesis; Constraint programmering;

    Abstract : With the increasing complexity of the chip architecture design for meeting different application requirements, the corresponding instruction scheduler of high-level synthesis tool needs to solve complex scheduling problems. Dynamically Reconfigurable Resource Array (DRRA) is a novel architecture based on Coarse-Grained Reconfigurable Architecture (CGRA) on SiLago platform, the instruction scheduler of Vesyla-II, the dedicated High-Level Synthesis (HLS) tool targets for DRRA needs to schedule the specific instruction sets designed for Distributed Two-level Control System (D2LC). READ MORE

  3. 2. A General Purpose Near Data Processing Architecture Optimized for Data-intensive Applications

    University essay from Lunds universitet/Institutionen för elektro- och informationsteknik

    Author : Xingda Li; Haidi Hu; [2023]
    Keywords : Technology and Engineering;

    Abstract : In recent years, as Internet of Things (IoT) and machine learning technologies have advanced, there has been increasing interest in the study of energy-efficient and flexible architectures for embedded systems. To bridge the performance gap between microprocessors and memory systems, Near-Data Processing (NDP) was introduced. READ MORE

  4. 3. Develop a Graphical User Interface for the assembler for SiLago Platform

    University essay from KTH/Skolan för elektroteknik och datavetenskap (EECS)

    Author : Yuxuan Wang; [2023]
    Keywords : Graphic intermediate representation; Graphical analytic system; High-level synthesis tool; Grafisk mellanrepresentationen; Grafiskt analytiskt system; Högnivå syntes verktyg;

    Abstract : Vesyla-II is developed as the High-Level Synthesis (HLS) tool serving the SiLago platform. The assembler Manas is a part of the Coarse Grain Reconfigurable Architectures (CGRA) compiler in Vesyla-II, which is used to transform the information from source code into the target language. READ MORE

  5. 4. Acoarse grain reconfigurable memory architecture for linear algebra and deep neural networks

    University essay from KTH/Skolan för elektroteknik och datavetenskap (EECS)

    Author : Cyril Armand Koenig; [2022]
    Keywords : ;

    Abstract : Companies and institutions around the world have been working to develop machines with always more computing power. This race has now found its new objective: hexascale computing (with 1018 flops machines). READ MORE

  6. 5. Mapping quantized convolutional layers on the SiLago platform

    University essay from KTH/Skolan för elektroteknik och datavetenskap (EECS)

    Author : Yue Zhang; [2022]
    Keywords : SiLago; algorithm mapping; quantized neural networks; convolution; SiLago; algoritmkartläggning; kvantiserade neurala nätverk; faltning;

    Abstract : Convolutional neural networks (CNNs) have been utilized in various applications, such as image classification, computer vision, etc. With development, the complexity and computation of CNNs also increase, which requires more memory and resources when deployed on devices, especially embedded systems. READ MORE