Essays about: "CPU Central Processing Unit"
Showing result 11 - 15 of 37 essays containing the words CPU Central Processing Unit.
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11. Development of a Light Weight L2-Cache Controller
University essay from Luleå tekniska universitet/RymdteknikAbstract : An L2 cache is a device that buffers data in fast memory closer to the Central Processing Unit(CPU) in order to deliver its contents with much lower latency than can otherwise be achieved bymain memory. This provides a substantial performance increase in many systems as the memoryinterface is often a bottleneck. READ MORE
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12. A FaaS Instance Management Algorithm for Minimizing Cost subject to Response Time
University essay from KTH/Skolan för elektroteknik och datavetenskap (EECS)Abstract : With the development of cloud computing technologies, the concept of Function as a Service (FaaS) has become increasingly popular over the years. Developers can choose to create applications in the form of functions, and delegate the deployment and management of the infrastructure to the FaaS provider. READ MORE
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13. Interactive Visualization of Air Traffic in OpenSpace
University essay from Linköpings universitet/Medie- och Informationsteknik; Linköpings universitet/Tekniska fakultetenAbstract : This thesis report presents a master’s thesis project in Media Technology by two students from Linköping University, Sweden. The project was implemented in collaboration with the Visualization Center C and Linköping University during the spring of 2021 resulting in the creation and development of two spatiotemporal visualizations featuring air traffic data in the OPENSPACE software. READ MORE
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14. Design and evaluation of an inter-core QUIC connection migration approach for intra-server load balancing
University essay from KTH/Skolan för elektroteknik och datavetenskap (EECS)Abstract : With the emergence of novel cloud applications and their critical latency demand [1], Quick UDP Internet Connection (QUIC) [2] was proposed as a new transport protocol that is promising to reduce the connection establishment overhead while providing security properties similar to Transport Layer Security (TLS) [3]. However, without an efficient task scheduling mechanism, the high cost for encryption and decryption in QUIC can easily lead to load imbalance among multiple Central Processing Unit (CPU) cores and thus cause a high tail latency. READ MORE
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15. Validating Side Channel models in RISC-V using Model-Based Testing
University essay from KTH/Skolan för elektroteknik och datavetenskap (EECS)Abstract : Microarchitecture’s optimizations have increased the performance but lowered the security. Speculative execution is one of the optimizations that was thought to be secure, but it is exploitable to leak information. READ MORE