Essays about: "CPU cache"

Showing result 1 - 5 of 31 essays containing the words CPU cache.

  1. 1. Diffuser: Packet Spraying While Maintaining Order : Distributed Event Scheduler for Maintaining Packet Order while Packet Spraying in DPDK

    University essay from KTH/Skolan för elektroteknik och datavetenskap (EECS)

    Author : Vignesh Purushotham Srinivas; [2023]
    Keywords : Packet scheduling; Scheduling; Out of order; Data plane development kit; Parallel processing; Network processor; Paketschemaläggning; Schemaläggning; oordning; Dataplansutvecklingskit; Parallell bearbetning; Nätverksprocessor;

    Abstract : The demand for high-speed networking applications has made Network Processors (NPs) and Central Computing Units (CPUs) increasingly parallel and complex, containing numerous on-chip processing cores. This parallelism can only be exploited fully by the underlying packet scheduler by efficiently utilizing all the available cores. READ MORE

  3. 2. Register Caching for Energy Efficient GPGPU Tensor Core Computing

    University essay from KTH/Skolan för elektroteknik och datavetenskap (EECS)

    Author : Qiran Qian; [2023]
    Keywords : Computer Architecture; GPGPU; Tensor Core; GEMM; Energy Efficiency; Register File; Cache; Instruction Scheduling; Datorarkitektur; GPGPU; Tensor Core; GEMM; energieffektivitet; registerfil; cache; instruktionsschemaläggning;

    Abstract : The General-Purpose GPU (GPGPU) has emerged as the predominant computing device for extensive parallel workloads in the fields of Artificial Intelligence (AI) and Scientific Computing, primarily owing to its adoption of the Single Instruction Multiple Thread architecture, which not only provides a wealth of thread context but also effectively hide the latencies exposed in the single threads executions. As computational demands have evolved, modern GPGPUs have incorporated specialized matrix engines, e. READ MORE

  4. 3. Development of a Light Weight L2-Cache Controller

    University essay from Luleå tekniska universitet/Rymdteknik

    Author : Måns Arildsson; [2022]
    Keywords : ;

    Abstract : An L2 cache is a device that buffers data in fast memory closer to the Central Processing Unit(CPU) in order to deliver its contents with much lower latency than can otherwise be achieved bymain memory. This provides a substantial performance increase in many systems as the memoryinterface is often a bottleneck. READ MORE

  5. 4. Network Implementation with TCP Protocol : A server on FPGA handling multiple connections

    University essay from KTH/Skolan för elektroteknik och datavetenskap (EECS)

    Author : Ruobing Li; [2022]
    Keywords : CPU Offloading; Ethernet; FPGA; TCP IP; Verilog; Xilinx 7 Series; CPU Avlastning; Ethernet; FPGA; TCP IP; Verilog; Xilinx 7 Series;

    Abstract : The growing number of players in Massively Multiplayer Online games puts a heavy load on the network infrastructure and the general-purpose CPU of the game servers. A game server’s network stack processing needs equal treatment to the game-related processing ability. READ MORE

  6. 5. Performance comparison between OOD and DOD with multithreading in games

    University essay from Blekinge Tekniska Högskola

    Author : David Wingqvist; Filip Wickström; [2022]
    Keywords : Game development; C ; Execution time; CPU cache; OpenMP;

    Abstract : Background. The frame rate of a game is important for both the end-user and the developer. Maintaining at least 60 FPS in a PC game is the current standard, and demands for efficient game applications rise. Currently, the industry standard within programming is to use Object-Oriented Design (OOD). READ MORE