Essays about: "DSP block"

Showing result 1 - 5 of 13 essays containing the words DSP block.

  1. 1. High Level Synthesis for ASIC and FPGA

    University essay from Lunds universitet/Institutionen för elektro- och informationsteknik

    Author : Malin Heyden; [2023]
    Keywords : HLS; high level synthesis; asic; fpga; catapult; filter; sfir; Technology and Engineering;

    Abstract : This thesis aims to evaluate the performance of Siemens’ High Level Synthesis (HLS) tool Catapult. HLS can be considered the next step up in abstraction level from writing traditional Register Transfer Level (RTL) code which is time consuming and error prone. READ MORE

  3. 2. Investigating and Modeling Uplink Processing in 5G NR Multisector Scheduler Simulator

    University essay from Lunds universitet/Institutionen för elektro- och informationsteknik

    Author : Oskar Nygren; Axel Sneitz-Björkman; [2022]
    Keywords : Technology and Engineering;

    Abstract : As the latest generation of wireless access technology called Fifth Generation (5G) New Radio (NR) evolves, computational efficiency is key to keep low cost and flexible deployments for vendors. Understanding how the Digital Signal Processing (DSP) load behaves in the digital units is one aspect to enable this efficiency. READ MORE

  4. 3. Power-Aware Software Development For EMCA DSP

    University essay from KTH/Skolan för informations- och kommunikationsteknik (ICT)

    Author : Meishenglan Zhang; [2017]
    Keywords : ;

    Abstract : The advent of FinFET technology necessitates a shift towards early dynamic power awareness, not only for ASIC block designers but also for software engineers that develop code for those blocks. CMOS dynamic power is typically reduced by optimizing the RTL models in terms of switching activity and clock gating efficiency. READ MORE

  5. 4. Turbo Code Performance Analysis Using Hardware Acceleration

    University essay from Linköpings universitet/Datorteknik

    Author : Oskar Nordmark; [2016]
    Keywords : Turbo code; hardware acceleration; digital signal processors; DSP; simulation; block error rate; BLER; pseudo random number generation; PRNG; 5G;

    Abstract : The upcoming 5G mobile communications system promises to enable use cases requiring ultra-reliable and low latency communications. Researchers therefore require more detailed information about aspects such as channel coding performance at very low block error rates. READ MORE

  6. 5. Distortion Cancellation in Time Interleaved ADCs

    University essay from Linköpings universitet/Elektroniska Kretsar och System

    Author : Naga Thejus Sambasivan Mruthyunjaya; [2015]
    Keywords : Time-Interleaved ADC; Post correction; Blind calibration; Harmonics cancellation; Mismatch analysis; Linearisation;

    Abstract : Time-Interleaved Analog to Digital Converters (TI ADC) consist of several individual sub-converters operating at a lower sampling rate, working in parallel, and in a circular loop. Thereby, they are increasing the sampling rate without compromising on the resolution during conversion, at high sampling rates. READ MORE