Essays about: "Delay-locked loop"
Found 5 essays containing the words Delay-locked loop.
-
1. Investigation of Analog Calibration Systems for Spurious Tone Suppression in Frequency Triplers
University essay from Lunds universitet/Institutionen för elektro- och informationsteknikAbstract : The market for Wi-Fi receiver designs for latest Wi-Fi standards, that cover RF bands in the 2.4 GHz, 5 GHz and 6 GHz spectrum, require increasingly stringent power consumption limitations as more of the market is driven towards battery-powered devices. READ MORE
-
2. DLL Based Reference Multiplier for the use in a PLL for WLAN applications
University essay from Lunds universitet/Fysiska institutionenAbstract : This master’s thesis project report deals with the design of multiplier for the reference signal to the Phase Locked Loop (PLL) used in WLAN application. The reference multiplier designed is based on a newly proposed architecture of dual loop feedback Delay Locked Loop (DLL) in which multiplication is performed within the loops. READ MORE
-
3. A Wide Range Low Power Low Jitter All Digital DLL for Video Applications
University essay from ElektroniksystemAbstract : Technological advancements in video technology have placed stringent requirements on video analog front ends (AFEs) to deliver high resolutions crisp images while consuming low power to deliver optimal performance. One of the vital parts of an AFE is a delay locked loop (DLL). READ MORE
-
4. A Sizing Algorithm for Non-Overlapping Clock Signal Generators
University essay from Institutionen för systemteknikAbstract : The non-overlapping clock signal generator circuits are key elements in switched capacitor circuits since non-overlapping clock signals are generally required. Non-overlapping clock signals means signals running at the same frequency and there is a time between the pulses that none of them is high. READ MORE
-
5. Delay-locked Loop : an adaptive timing alignment
University essay from Blekinge Tekniska Högskola/Institutionen för signalbehandlingAbstract : Conventional approches to the problem of extracting a clock from the data do not automatically hold the clock in the center of the data-eye. This thesis describes a data feedback technique that adjusts the clock and significantly reduces timing uncertainty by compensating for initial ciruit misalignment, propagation delay variations and low-frequency jitter. READ MORE
