Essays about: "FPGA design workflow"

Found 3 essays containing the words FPGA design workflow.

  1. 1. Implementation of a Deep Learning Inference Accelerator on the FPGA.

    University essay from Lunds universitet/Institutionen för elektro- och informationsteknik

    Author : Shenbagaraman Ramakrishnan; [2020]
    Keywords : Artificial Intelligence; Machine Learning; Deep Learning; Neural Networks; Deep Learning Accelerators; NVDLA; FPGA; Technology and Engineering;

    Abstract : Today, Artificial Intelligence is one of the most important technologies, ubiquitous in our daily lives. Deep Neural Networks (DNN's) have come up as state of art for various machine intelligence applications such as object detection, image classification, face recognition and performs myriad of activities with exceptional prediction accuracy. READ MORE

  2. 2. Evaluation of high-level synthesis tools for generation of Verilog code from MATLAB based environments

    University essay from Luleå tekniska universitet/Institutionen för system- och rymdteknik

    Author : Carl Bäck; [2020]
    Keywords : HLS; System Generator for DSP; Histogram; Xilinx Zynq UltraScale ; FPGA design workflow; Hardware Description Language Coder; HDL Coder; Field Programmable Gate Arrays; Image processing;

    Abstract : FPGAs are of interest in the signal processing domain as they provide the opportunity to run algorithms at very high speed. One possible use case is to sort incoming data in a measurement system, using e.g. a histogram method. READ MORE

  3. 3. Performance Evaluation of MathWorks HDL Coder as a Vendor Independent DFE Generation

    University essay from Lunds universitet/Institutionen för elektro- och informationsteknik

    Author : Elisabeth Pongratz; Roshan Cherian John; [2019]
    Keywords : MATLAB; Simulink; HDL Coder; XSG; DSPB; Technology and Engineering;

    Abstract : This thesis aims to evaluate MathWorks HDL (Hardware Descriptive Language) Coder and compare the results with designs produced by its vendor dependent counterparts. The focus is mainly on evaluate the design effort needed to close timing and to get optimal resource mapping for a selected design. READ MORE