Essays about: "HLS"

Showing result 1 - 5 of 33 essays containing the word HLS.

  1. 1. Optimizing on-chip Machine Learning for Data Prefetching

    University essay from Göteborgs universitet/Institutionen för data- och informationsteknik

    Author : Hampus Larsson; Miranda Jernberg; Albin Pansell; Fabian Stigsson; Fredrik Hamrefors; Pontus Söderström; [2023-03-03]
    Keywords : Data Prefetching; Machine Learning; HW SW co-Design; HLS; FPGA;

    Abstract : The idea behind data prefetching is to speed up program execution by predicting what data is needed by the processor, before it is actually needed. Data prefetching is commonly performed by prefetching the next memory address in line, but there are other, more sophisticated approaches such as machine learning. READ MORE

  2. 2. Optimizing the instruction scheduler of high-level synthesis tool

    University essay from KTH/Skolan för elektroteknik och datavetenskap (EECS)

    Author : Zihao Xu; [2023]
    Keywords : Instruction scheduling; Scheduling algorithm; CGRA; High-level Sythnesis; SiLago; Algorithm-level Synthesis; Constraint programming; Instruktion schemaläggning; schemaläggning algoritm; CGRA; High-level Sythnesis; SiLago; Algoritm-nivå Synthesis; Constraint programmering;

    Abstract : With the increasing complexity of the chip architecture design for meeting different application requirements, the corresponding instruction scheduler of high-level synthesis tool needs to solve complex scheduling problems. Dynamically Reconfigurable Resource Array (DRRA) is a novel architecture based on Coarse-Grained Reconfigurable Architecture (CGRA) on SiLago platform, the instruction scheduler of Vesyla-II, the dedicated High-Level Synthesis (HLS) tool targets for DRRA needs to schedule the specific instruction sets designed for Distributed Two-level Control System (D2LC). READ MORE

  3. 3. Novel Method of ASIC interface IP development using HLS

    University essay from Lunds universitet/Institutionen för elektro- och informationsteknik

    Author : Anestis Athanasiadis; Chandranshu Mishra; [2023]
    Keywords : High Level Synthesis; HLS; Untimed C ; Control logic; I3C; clock-accurate design; IP development; Technology and Engineering;

    Abstract : High-Level Synthesis(HLS) is a design methodology that enables designers to implement hardware from high-level coding languages, such as C, C++, or System C. It provides designers with the ability to convey their design at a higher level of abstraction, which allows more emphasis on an algorithm and functional aspects of design instead on low-level hardware details. READ MORE

  4. 4. Develop a Graphical User Interface for the assembler for SiLago Platform

    University essay from KTH/Skolan för elektroteknik och datavetenskap (EECS)

    Author : Yuxuan Wang; [2023]
    Keywords : Graphic intermediate representation; Graphical analytic system; High-level synthesis tool; Grafisk mellanrepresentationen; Grafiskt analytiskt system; Högnivå syntes verktyg;

    Abstract : Vesyla-II is developed as the High-Level Synthesis (HLS) tool serving the SiLago platform. The assembler Manas is a part of the Coarse Grain Reconfigurable Architectures (CGRA) compiler in Vesyla-II, which is used to transform the information from source code into the target language. READ MORE

  5. 5. High Level Synthesis for ASIC and FPGA

    University essay from Lunds universitet/Institutionen för elektro- och informationsteknik

    Author : Malin Heyden; [2023]
    Keywords : HLS; high level synthesis; asic; fpga; catapult; filter; sfir; Technology and Engineering;

    Abstract : This thesis aims to evaluate the performance of Siemens’ High Level Synthesis (HLS) tool Catapult. HLS can be considered the next step up in abstraction level from writing traditional Register Transfer Level (RTL) code which is time consuming and error prone. READ MORE