Essays about: "Hardware Accelerator for Duo-binary CTC decoding – Algorithm selection"

Found 1 essay containing the words Hardware Accelerator for Duo-binary CTC decoding – Algorithm selection.

  1. 1. Hardware Accelerator for Duo-binary CTC decoding : Algorithm Selection, HW/SW Partitioning and FPGA Implementation

    University essay from Institutionen för systemteknik

    Author : Joakim Bjärmark; Marco Strandberg; [2006]
    Keywords : Error Correcting Codes; Turbo Codes; Decoding; Implementation; FPGA;

    Abstract : Wireless communication is always struggling with errors in the transmission. The digital data received from the radio channel is often erroneous due to thermal noise and fading. The error rate can be lowered by using higher transmission power or by using an effective error correcting code. READ MORE