Essays about: "High level synthesis"
Showing result 16 - 20 of 94 essays containing the words High level synthesis.
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16. Implementation of Bolt Detection and Visual-Inertial Localization Algorithm for Tightening Tool on SoC FPGA
University essay from KTH/Skolan för elektroteknik och datavetenskap (EECS)Abstract : With the emergence of Industry 4.0, there is a pronounced emphasis on the necessity for enhanced flexibility in assembly processes. In the domain of bolt-tightening, this transition is evident. Tools are now required to navigate a variety of bolts and unpredictable tightening methodologies. READ MORE
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17. Using Symmetry for Realistic Virtual Living Room Generation : Generating virtual layouts
University essay from KTH/Skolan för elektroteknik och datavetenskap (EECS)Abstract : Procedurell generering är en teknik som används inom dataspel och annan programvara för att generera innehåll algoritmiskt snarare än manuellt. I detta projekt utökas metoden av Kán och Kaufmann (2018) för att procedurellt generera trovärdiga, virtuella scenlayouter till att använda reflekterande symmetri för syntes [14]. READ MORE
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18. Evaluation of strategies for construction of protease libraries in yeast.
University essay from Lunds universitet/Teknisk mikrobiologi; Lunds universitet/BioteknikAbstract : Proteases are a group of enzymes that are involved in breaking down larger proteins into smaller polypeptides or single amino acids, and they are used in various applications. In this project, the potential of budding yeast Saccharomyces cerevisiae as host for the construction of protease libraries is evaluated. READ MORE
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19. Structural Dynamics at Higher Frequencies using the Finite Element Method : Assessment of Solver Algorithms and Component Mode Synthesis for Dynamic Response Analysis of Large Structures
University essay from KTH/HållfasthetsläraAbstract : Scania is making a transition from traditional combustion engines to electric vehicles and therefore developing methodology for high frequency analysis of large structures. The computational time size of results files are impractically high, making any analysis infeasible. READ MORE
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20. Using HLS for Acceleration of FPGA Development: A 3780-Point FFT Case Study
University essay from Linköpings universitet/Datorteknik; Linköpings universitet/Tekniska fakultetenAbstract : Manually designing hardware for fpga implementations is time consuming. Onepossible way to accelerate the development of hardware is to use high level syn-thesis (hls) tools. Such tools synthesizes a high level model written in a languagesuch as c++ into hardware. READ MORE