Essays about: "High-level Synthesis"

Showing result 1 - 5 of 55 essays containing the words High-level Synthesis.

1. 1. Deep Learning Model Deployment for Spaceborne Reconfigurable Hardware : A flexible acceleration approach

   University essay from KTH/Skolan för elektroteknik och datavetenskap (EECS)

   Author : Javier Ferre Martin; [2023]
   Keywords : Space Situational Awareness; Deep Learning; Convolutional Neural Networks; FieldProgrammable Gate Arrays; System-On-Chip; Computer Vision; Dynamic Partial Reconfiguration; High-Level Synthesis; Rymdsituationstänksamhet; Djupinlärning; Konvolutionsnätverk; Omkonfigurerbara Field-Programmable Gate Arrays FPGAs ; System-On-Chip SoC ; Datorseende; Dynamisk partiell omkonfigurering; Högnivåsyntes.;

   Abstract : Space debris and space situational awareness (SSA) have become growing concerns for national security and the sustainability of space operations, where timely detection and tracking of space objects is critical in preventing collision events. Traditional computer-vision algorithms have been used extensively to solve detection and tracking problems in flight, but recently deep learning approaches have seen widespread adoption in non-space related applications for their high accuracy. READ MORE

3. 2. Code Synthesis for Heterogeneous Platforms

   University essay from KTH/Skolan för elektroteknik och datavetenskap (EECS)

   Author : Zhouxiang Fu; [2023]
   Keywords : Code Synthesis; Heterogeneous Platform; Zero-Overhead Topology Infrastructure; Kodsyntes; Heterogen plattform; Zero-Overhead Topologi Infrastruktur;

   Abstract : Heterogeneous platforms, systems with both general-purpose processors and task-specific hardware, are largely used in industry to increase efficiency, but the heterogeneity also increases the difficulty of design and verification. We often need to wait for the completion of all the modules to know whether the functionality of the design is correct or not, which can cause costly and tedious design iteration cycles. READ MORE

4. 3. Optimizing the instruction scheduler of high-level synthesis tool

   University essay from KTH/Skolan för elektroteknik och datavetenskap (EECS)

   Author : Zihao Xu; [2023]
   Keywords : Instruction scheduling; Scheduling algorithm; CGRA; High-level Sythnesis; SiLago; Algorithm-level Synthesis; Constraint programming; Instruktion schemaläggning; schemaläggning algoritm; CGRA; High-level Sythnesis; SiLago; Algoritm-nivå Synthesis; Constraint programmering;

   Abstract : With the increasing complexity of the chip architecture design for meeting different application requirements, the corresponding instruction scheduler of high-level synthesis tool needs to solve complex scheduling problems. Dynamically Reconfigurable Resource Array (DRRA) is a novel architecture based on Coarse-Grained Reconfigurable Architecture (CGRA) on SiLago platform, the instruction scheduler of Vesyla-II, the dedicated High-Level Synthesis (HLS) tool targets for DRRA needs to schedule the specific instruction sets designed for Distributed Two-level Control System (D2LC). READ MORE

5. 4. Novel Method of ASIC interface IP development using HLS

   University essay from Lunds universitet/Institutionen för elektro- och informationsteknik

   Author : Anestis Athanasiadis; Chandranshu Mishra; [2023]
   Keywords : High Level Synthesis; HLS; Untimed C ; Control logic; I3C; clock-accurate design; IP development; Technology and Engineering;

   Abstract : High-Level Synthesis(HLS) is a design methodology that enables designers to implement hardware from high-level coding languages, such as C, C++, or System C. It provides designers with the ability to convey their design at a higher level of abstraction, which allows more emphasis on an algorithm and functional aspects of design instead on low-level hardware details. READ MORE

6. 5. Low-power Acceleration of Convolutional Neural Networks using Near Memory Computing on a RISC-V SoC

   University essay from Lunds universitet/Institutionen för elektro- och informationsteknik

   Author : Kristoffer Westring; Linus Svensson; [2023]
   Keywords : FPGA; ASIC; Near Memory Computing; RISC-V; Convolutional Neural Network; Technology and Engineering;

   Abstract : The recent peak in interest for artificial intelligence, partly fueled by language models such as ChatGPT, is pushing the demand for machine learning and data processing in everyday applications, such as self-driving cars, where low latency is crucial and typically achieved through edge computing. The vast amount of data processing required intensifies the existing performance bottleneck of the data movement. READ MORE