Essays about: "INL"

Showing result 1 - 5 of 7 essays containing the word INL.

  1. 1. Design of a 12-bit 200-MSps SAR Analog-to-Digital converter

    University essay from KTH/Skolan för elektroteknik och datavetenskap (EECS)

    Author : Luca Ricci; [2020]
    Keywords : ;

    Abstract : The Successive Approximation (SAR) Analog-to-Digital converter is one of the most energy-efficient A/D converter. In this thesis, the development of a SAR ADC in a 28-nm CMOS technology based on charge redistribution is presented. READ MORE

  3. 2. Built-in self-test of analog-to-digital converters in FPGAs

    University essay from Linköpings universitet/Elektroniksystem

    Author : Petter Nilsson; [2014]
    Keywords : FPGA; BIST; ADC; dynamic test; static test; linearity; DNL; INL; offset; gain error; FFT; SNR; THD; delta-sigma; sigma-delta; DAC; high-level synthesis; HLS; IEEE Standard 1241;

    Abstract : When designing an ADC it is desirable to test its performance at two different points in the development process. The first is characterization and verification testing when a chip containing the ADC has been taped-out for the first time, and the second is production testing when the chip is manufactured in large scale. READ MORE

  4. 3. Design and Implementation of a Digitally Compensated N-Bit C-xC SAR ADC Model : Optimization of an Eight-Bit C-xC SAR ADC

    University essay from Elektroniksystem; Tekniska högskolan

    Author : Claes Hallström; [2013]
    Keywords : adc; sar; digital calibration;

    Abstract : In this master’s thesis a model of a digitally compensated N-bit C-xC sar adc was developed.The architecture uses charge redistribution in a C-xC capacitor network to performthe conversion. Focus in the master’s thesis was set to understand how the charge is redistributedin the network during the conversion and calibration phase. READ MORE

  5. 4. Multi-Path Dierential Delay Line based Time-to-Digital Converter for ADPLL

    University essay from KTH/Skolan för informations- och kommunikationsteknik (ICT)

    Author : XIAOLONG CHEN; [2013]
    Keywords : ;

    Abstract : All digital phase-locked loops (ADPLLs) play an important role in contemporary applications such as Bluetooth, GSM, WCDAM and WiFi. A timeto-digital converter (TDC) is the critical part in the ADPLL, usually the dominant quantization noise contributor. The quantization noise is caused by the nite resolution of the TDC. READ MORE

  6. 5. A Study of Output Impedance Effects in Current-Steering Digital-to-Analog Converters

    University essay from Elektroniksystem; Tekniska högskolan

    Author : AlajaKumari Sadda; Niraja Madavaneri; [2013]
    Keywords : Unit element; Current mirror; pole-zero analysis of unit-element; SFDR;

    Abstract : In this thesis, we have explained the different types of DAC (Digital-to-Analog) architectures and their advantages and disadvantages. We have mainly focused on current-steering digital-to-analog design for achieving high speed and high performance. The current-steering DAC is designed using binary weighted architecture. READ MORE