Essays about: "Jitter and phase noise"
Showing result 1 - 5 of 7 essays containing the words Jitter and phase noise.
-
1. A Digital Phase-Locked Loop for Frequency Synthesis using an Adaptive Pulse Shrinking TDC
University essay from Lunds universitet/Institutionen för elektro- och informationsteknikAbstract : This thesis investigates a new type of Phase-Locked Loop (PLL) architecture which combines a phase/frequency detector (PFD) and a digital loop filter. The quantization is done by a time-to-digital converter which continuously shrinks the pulse coming from the PFD and registers how far it propagates. READ MORE
-
2. A digital integer-N PLL architecture using a pulse-shrinking TDC for mmWave applications.
University essay from KTH/Skolan för elektroteknik och datavetenskap (EECS)Abstract : With the move of the broadband cellular network towards 5G taking off and the preparatory work on 6G and beyond starting, the need for low-complexity, low-power, and high-performance frequency synthesis using Phase-Locked Loop (PLL)s increases. As we get deeper into the mm-wave frequencies and push towards frequencies in the order of 50-70 GHz design challenges with existing PLL architectures, such as limited technology scaling and limited in-band noise performance become more apparent. READ MORE
-
3. PLL for 5G mmWave
University essay from Lunds universitet/Institutionen för elektro- och informationsteknikAbstract : This paper presents research and implementation of a high frequency Integer-N phase-locked loop for digital beamforming in mobile devices. Multiple topologies investigated whereof two were implemented. The transient phase noise of the PLL is -104dB/-95dB @1MHz. The output frequency range is from 8G-10G. READ MORE
-
4. System Level Modeling and Verification of All-digital Phase-locked Loop
University essay from KTH/Skolan för informations- och kommunikationsteknik (ICT)Abstract : In wirelesscommunication systems, a local oscillator (LO) aims at demodulating radio-frequency signals into baseband signals. The performance of these signals determines the quality of communications which is highly affected by the phase accuracy of local oscillators. READ MORE
-
5. DLL Based Reference Multiplier for the use in a PLL for WLAN applications
University essay from Lunds universitet/Fysiska institutionenAbstract : This master’s thesis project report deals with the design of multiplier for the reference signal to the Phase Locked Loop (PLL) used in WLAN application. The reference multiplier designed is based on a newly proposed architecture of dual loop feedback Delay Locked Loop (DLL) in which multiplication is performed within the loops. READ MORE
