Essays about: "Nätverk-på-Chip"

Found 4 essays containing the word Nätverk-på-Chip.

  1. 1. The Global Interconnection Scheme of Silago : RTL Design and Verification

    University essay from KTH/Skolan för elektroteknik och datavetenskap (EECS)

    Author : Tong Lou; [2023]
    Keywords : Silago; global interconnection; synchronous dataflow; network on chip; Silago; global sammankoppling; synkront dataflöde; nätverk på chip;

    Abstract : The Silago concept introduces a hardware-centric platform that is based on coarse-grained reconfigurable fabrics and networks on chips(NoCs). With the intra-region and inter-region NoC, the Silago platform can form resource clusters to host various applications. READ MORE

  2. 2. Mapping DNNs onto the NoC Platform

    University essay from KTH/Skolan för elektroteknik och datavetenskap (EECS)

    Author : Hanbo Xu; [2022]
    Keywords : ;

    Abstract : This thesis uses an existing NoC simulation platform to construct a Network on Chip-based many-core system. The network is an 8_8 mesh topology. This thesis chooses LeNet5, ResNet, VGGNet, and AlexNet as the computing load, and tries to obtain a deep neural network mapping algorithm based on a NoC design method that can be widely used. READ MORE

  3. 3. Design of the SiLago GNOC

    University essay from KTH/Skolan för elektroteknik och datavetenskap (EECS)

    Author : Weiyao Tang; [2022]
    Keywords : Synchoros Blocks; SiLago models; Network on Chips; Routing Algorithm and Deadlock; Physical Design; Synchoros-block; SiLago-modeller; nätverk på chip; routingalgoritm och dödläge; fysisk design;

    Abstract : Synchoros VLSI design style can be an alternative choice to fit the increasing complexity of embedded multi-processor architectures. SiLago Block is part of the synchoros blocks, which can effectively reduce the cost of logic and physical synthesis as it is hardened and highly centralized details from each layer of metal. READ MORE

  4. 4. A Specification for Time-Predictable Communication on TDM-based MPSoC Platforms

    University essay from KTH/Skolan för elektroteknik och datavetenskap (EECS)

    Author : Kelun Liu; [2021]
    Keywords : Communication; Time-Predictability; Network-on-Chip; Software Specification; Worst-Case Communication Time; Kommunikation; Tid Förutsägbarhet; Nätverk-på-Chip; MjukvaruSpecifikation; Kommunikationstid i Värsta Fall;

    Abstract : Formal System Design (ForSyDe) aims to bring the design of multiprocessor systems-on-chip (MPSoCs) to a higher level of abstraction and bridge the abstraction gap by transformational design refinement. The current research is focused on a correct-by-construction design flow, which requires design space exploration including formal models of computation and timepredictable platforms. READ MORE