Essays about: "Register allocation"

Showing result 1 - 5 of 14 essays containing the words Register allocation.

1. 1. Machine Learning-Based Instruction Scheduling for a DSP Architecture Compiler : Instruction Scheduling using Deep Reinforcement Learning and Graph Convolutional Networks

   University essay from KTH/Skolan för elektroteknik och datavetenskap (EECS)

   Author : Lucas Alava Peña; [2023]
   Keywords : Instruction Scheduling; Deep reinforcement Learning; Compilers; Graph Convolutional Networks; Schemaläggning av instruktioner; Deep Reinforcement Learning; kompilatorer; grafkonvolutionella nätverk;

   Abstract : Instruction Scheduling is a back-end compiler optimisation technique that can provide significant performance gains. It refers to ordering instructions in a particular order to reduce latency for processors with instruction-level parallelism. READ MORE

3. 2. Register Caching for Energy Efficient GPGPU Tensor Core Computing

   University essay from KTH/Skolan för elektroteknik och datavetenskap (EECS)

   Author : Qiran Qian; [2023]
   Keywords : Computer Architecture; GPGPU; Tensor Core; GEMM; Energy Efficiency; Register File; Cache; Instruction Scheduling; Datorarkitektur; GPGPU; Tensor Core; GEMM; energieffektivitet; registerfil; cache; instruktionsschemaläggning;

   Abstract : The General-Purpose GPU (GPGPU) has emerged as the predominant computing device for extensive parallel workloads in the fields of Artificial Intelligence (AI) and Scientific Computing, primarily owing to its adoption of the Single Instruction Multiple Thread architecture, which not only provides a wealth of thread context but also effectively hide the latencies exposed in the single threads executions. As computational demands have evolved, modern GPGPUs have incorporated specialized matrix engines, e. READ MORE

4. 3. Adapting a Constraint-Based Compiler Tool to a New VLIW Architecture

   University essay from Uppsala universitet/Institutionen för informationsteknologi

   Author : Martin Kjellin; [2019]
   Keywords : ;

   Abstract : he compiler tool Unison uses combinatorial optimisation to perform integrated register allocation and instruction scheduling, and is designed to be possible to adapt to different processor architectures. Black Arrow is a VLIW (very long instruction word) architecture designed for signal processing within the field of mobile communication technology. READ MORE

5. 4. A Systematic Approach to Automated Software Diversity Using Unison

   University essay from KTH/Skolan för elektroteknik och datavetenskap (EECS)

   Author : Patrik Karlström; [2018]
   Keywords : ;

   Abstract : Unison is a tool that combines instruction scheduling and register allocation as a single combinatorial problem and solves it using constraint programming, which is a programming paradigm for systematically solving combinatorial problems. Automated software diversity is the process of automatically providing diverse executables in an effort to break so called gadgets, which are short instruction sequences that together make up an attack vector. READ MORE

6. 5. Develop and prototype code generation techniques for a clause-based GPU

   University essay from Lunds universitet/Institutionen för datavetenskap

   Author : Johan Ju; Niklas Jonsson; [2017]
   Keywords : Code generation; GPU; Register allocation; Instruction scheduling; Compiler optimization; Technology and Engineering;

   Abstract : Processors grow more and more complex, even more so in the field of GPUs, where the instruction set, in general, is not publicly available. This enables them to change more rapidly than CPUs, since backwards compatibility is not an issue. In this thesis multiple approaches are investigated for code generation for a clause-based GPU. READ MORE