Essays about: "SOC Verification"

Showing result 1 - 5 of 14 essays containing the words SOC Verification.

  1. 1. Investigating Machine Learning for verification of AMBA APB protocol.

    University essay from Lunds universitet/Institutionen för elektro- och informationsteknik

    Author : Abhiram Srisai Kishore; Mohammed Wasim; [2022]
    Keywords : Machine learning; SOC Verification; AMBA; Neural Networks; Deep Learning; Assertions.; Technology and Engineering;

    Abstract : It is a well-known fact that in any Application Specific Integrated Circuit (ASIC) design, verification consumes most time and resources. And when it comes to huge designs, finding bugs can be tedious given the area and the complexity. As per Moore’s law, the design complexity is increasing exponentially due to the growing demand for performance. READ MORE

  2. 2. Energy efficient Ericsson Many-Core Architecture (EMCA) IP blocks for 5G ASIC

    University essay from Lunds universitet/Institutionen för elektro- och informationsteknik

    Author : Zilin Zhang; [2021]
    Keywords : Technology and Engineering;

    Abstract : Power consumption has become a leading concern for SoC aimed at 5G products that demand increased functionality, smaller form factors, and low energy footprint. For some EMCA IP blocks a hierarchical clock gating mechanism ensures coarse-grained power savings based on actual processing need but for many blocks this approach cannot be employed. READ MORE

  3. 3. Low power memory controller subsystem IP exploration using RTL power flow : An End-to-end power analysis and reduction Methodology

    University essay from KTH/Skolan för elektroteknik och datavetenskap (EECS)

    Author : Neerajnayan Balachandran; [2020]
    Keywords : Power analysis; Block characterization; Optimization; Differential Energy analysis; Dynamic Power; Clock gating.; Power-analys; Block karakterisering; Optimering; Differential Energy-analys; Dynamic Power; Clock gating;

    Abstract : With FinFET based Application Specific Integrated Circuit (ASIC) designs delivering on the promises of scalability, performance, and power, the road ahead is bumpy with technical challenges in building efficient ASICs. Designers can no longer rely on the ‘auto-scaling’ power reduction that follows technology node scaling, in these times when 7nm presents itself as a ‘long-lived’ node. READ MORE

  4. 4. Spice Circuit Reduction for Speeding up Simulation and Verification

    University essay from Lunds universitet/Institutionen för elektro- och informationsteknik

    Author : Menglin Wang; Cancan Yin; [2019]
    Keywords : Technology and Engineering;

    Abstract : The focus of this work has been to implement a generic netlist reduction engine to speed up circuit simulations. The netlist reduction techniques are further optimized for Static Random-Access Memory (SRAM), wherein we exploit the repetitive pattern of the circuit. READ MORE

  5. 5. A Technology Agnostic Approach for Standard-cell Layout Design Automation

    University essay from Lunds universitet/Institutionen för elektro- och informationsteknik

    Author : Tom Johansson; [2019]
    Keywords : IC; automation; standard cell; standard cell design; ASIC; chip; graph theory; SAT; full adder; adder; MUX; layout; schematic; mst; minimum spanning tree; kruskal; pnr; placement; routing; Technology and Engineering;

    Abstract : The logic scaling following Moores law has reached a level where System on Chips (SoCs) commonly contains millions of standard cells. The sheer amount implies that even small optimizations on a standard cell can have a significant effect on the SoC performance. To ensure the performance of standard cells, many of these are hand-drawn. READ MORE