Essays about: "SOC Verification"
Showing result 1 - 5 of 15 essays containing the words SOC Verification.
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1. Investigating Machine Learning for verification of AMBA APB protocol.
University essay from Lunds universitet/Institutionen för elektro- och informationsteknikAbstract : It is a well-known fact that in any Application Specific Integrated Circuit (ASIC) design, verification consumes most time and resources. And when it comes to huge designs, finding bugs can be tedious given the area and the complexity. As per Moore’s law, the design complexity is increasing exponentially due to the growing demand for performance. READ MORE
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2. Configurable, scalable single-ended sense amplifier with additional auxiliary blocks for low-power two-port memories in advanced FinFET technologies
University essay from Lunds universitet/Institutionen för elektro- och informationsteknikAbstract : System on Chip (SoC) designs contain a variety of Intellectual Property (IP) cores, including digital signal processing blocks, media and graphics processing units, as well as processing core units that employ multiple-port memories to enhance performance and bandwidth. These memories allow parallel read/write operations from the same memory blocks from different ports. READ MORE
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3. Energy efficient Ericsson Many-Core Architecture (EMCA) IP blocks for 5G ASIC
University essay from Lunds universitet/Institutionen för elektro- och informationsteknikAbstract : Power consumption has become a leading concern for SoC aimed at 5G products that demand increased functionality, smaller form factors, and low energy footprint. For some EMCA IP blocks a hierarchical clock gating mechanism ensures coarse-grained power savings based on actual processing need but for many blocks this approach cannot be employed. READ MORE
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4. Low power memory controller subsystem IP exploration using RTL power flow : An End-to-end power analysis and reduction Methodology
University essay from KTH/Skolan för elektroteknik och datavetenskap (EECS)Abstract : With FinFET based Application Specific Integrated Circuit (ASIC) designs delivering on the promises of scalability, performance, and power, the road ahead is bumpy with technical challenges in building efficient ASICs. Designers can no longer rely on the ‘auto-scaling’ power reduction that follows technology node scaling, in these times when 7nm presents itself as a ‘long-lived’ node. READ MORE
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5. Spice Circuit Reduction for Speeding up Simulation and Verification
University essay from Lunds universitet/Institutionen för elektro- och informationsteknikAbstract : The focus of this work has been to implement a generic netlist reduction engine to speed up circuit simulations. The netlist reduction techniques are further optimized for Static Random-Access Memory (SRAM), wherein we exploit the repetitive pattern of the circuit. READ MORE
