Essays about: "SystemVerilog"

Showing result 1 - 5 of 13 essays containing the word SystemVerilog.

  1. 1. Content assist in integrated development environments for hardware description languages

    University essay from KTH/Skolan för elektroteknik och datavetenskap (EECS)

    Author : David Nadjar; [2023]
    Keywords : SystemVerilog; Content assist; Auto-completion; Hardware Development Language HDL ; Sigasi; Eclipse; Ordering; SystemVerilog; Content assist; Automatisk komplettering; Hårdvarubeskrivningsspråk HDL ; Sigasi; Eclipse; Ordning;

    Abstract : Content assist is one of the most powerful features in integrated development environments (IDE). While a lot of research papers exist on content assist for software programming languages (SPL), hardware description languages (HDL) aren’t covered at all. READ MORE

  3. 2. Modularity, Scalability, Reusability, Configurability, and Interoperability of ASIC/FPGA Verification IP

    University essay from KTH/Skolan för elektroteknik och datavetenskap (EECS)

    Author : Trupti Rao; [2022]
    Keywords : Verification Intellectual Property; UniversalVerification Methodology; Avalon Streaming Interface; Object-oriented Programming;

    Abstract : The complexity of chip design has been exponentially rising, resulting in increased complexity and costs in chip verification. This rise in complexity results in increased time to market and increases risks of chip in fabrication, that can be catastrophic and result in major losses. READ MORE

  4. 3. Design a Three-Stage Pipelined RISC-V Processor Using SystemVerilog

    University essay from KTH/Skolan för elektroteknik och datavetenskap (EECS)

    Author : Ziyan He; [2022]
    Keywords : RISC; RISC-V; ISA; SystemVerilog; RTL simulation; RV32IM; CPI; RISC; RISC-V; ISA; SystemVerilog; RTL simulering; RV32IM; CPI;

    Abstract : RISC-V is growing in popularity as a free and open RISC Instruction Set Architecture (ISA) in academia and research. Also, the openness, simplicity, extensibility, and modularity, among its advantages, make it more and more used by designers in industry. The aim of this thesis is to design an open-source RISC-V processor. READ MORE

  5. 4. Development of a new verification environment for a GPU hardware block using the Universal Verification Methodology

    University essay from Lunds universitet/Institutionen för elektro- och informationsteknik

    Author : Niklas Karlsson; [2020]
    Keywords : Technology and Engineering;

    Abstract : The invention of the integrated circuit is a key milestone in the history of electronic circuits. Since its introduction the number of components on a chip have increased rapidly, making them more powerful and able to perform complex operations, but it has also changed the design process. READ MORE

  6. 5. Case study on Universal Verification Methodology(UVM) SystemC testbench for RTL verification

    University essay from Lunds universitet/Institutionen för elektro- och informationsteknik

    Author : Kevin Skaria Chacko; [2019]
    Keywords : Technology and Engineering;

    Abstract : This Master’s thesis aims to conduct a case study on using Universal Verification Methodology (UVM) in SystemC for Register-Transfer Level (RTL) verification. Verification of ASICs is very important nowadays especially in terms of production costs, time to market and the sustainability of products. READ MORE