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Showing result 1 - 5 of 28 essays matching the above criteria.

  1. 1. A Digital Phase-Locked Loop for Frequency Synthesis using an Adaptive Pulse Shrinking TDC

    University essay from Lunds universitet/Institutionen för elektro- och informationsteknik

    Author : Viktor Lewin; [2023]
    Keywords : Phase-locked loop; PLL; DPLL; Frequency Synthesis; TDC; PFD; Technology and Engineering;

    Abstract : This thesis investigates a new type of Phase-Locked Loop (PLL) architecture which combines a phase/frequency detector (PFD) and a digital loop filter. The quantization is done by a time-to-digital converter which continuously shrinks the pulse coming from the PFD and registers how far it propagates. READ MORE

  2. 2. 3D CFD Simulations of Hydrogen Engine Combustion

    University essay from Lunds universitet/Institutionen för energivetenskaper

    Author : Hao Liu; [2023]
    Keywords : Technology and Engineering;

    Abstract : With the trend of decarbonization, the transport sector is exploring possibilities of fossil fuel free solutions. Hydrogen can be a potential fuel for future engine applications. In this work, the concept of H2 HPDI is investigated, where a pilot diesel injection ignites the hydrogen jet. READ MORE

  3. 3. A digital integer-N PLL architecture using a pulse-shrinking TDC for mmWave applications.

    University essay from KTH/Skolan för elektroteknik och datavetenskap (EECS)

    Author : Simon Richter; [2023]
    Keywords : Phase-locked-loops; All-digital Phase-locked-loops; Time-to-digital converters; 5G and beyond; Radio-frequency design; Fas-låsd-loop; Helt-digital fas-låst-loop; Tid-till-digital-omvandlare; 5G och framtiden; Radio-frekvens design;

    Abstract : With the move of the broadband cellular network towards 5G taking off and the preparatory work on 6G and beyond starting, the need for low-complexity, low-power, and high-performance frequency synthesis using Phase-Locked Loop (PLL)s increases. As we get deeper into the mm-wave frequencies and push towards frequencies in the order of 50-70 GHz design challenges with existing PLL architectures, such as limited technology scaling and limited in-band noise performance become more apparent. READ MORE

  4. 4. A 1.8 ps Time-to-Digital Converter (TDC) Implemented in a 20 nm Field-Programmable Gate Array (FPGA) Using a Ones-Counter Encoding Scheme with Embedded Bin-Width Calibrations and Temperature Correction

    University essay from Linköpings universitet/Datorteknik

    Author : Engström Sven; [2020]
    Keywords : time-to-digital; time-to-digital converter; TDC; 1.8 ps; field-programmable gate array; FPGA; 20 nm; Xilinx; Kintex; UltraScale; tapped delay line; TDL; taps; carry-chain; ones-counter; bit-counter; bubbles; wave-union; embedded; temperature correction;

    Abstract : This thesis investigates the use of field-programmable gate arrays (FPGAs) to implement a time-to-digital converter (TDC) with on-chip calibration and temperature correction.Using carry-chains on the Xilinx Kintex UltraScale architecture to create a tapped delay line (TDL) has previously been proven to give good time resolution. READ MORE

  5. 5. Trace level analyses of selected perfluoroalkyl substancesin food: Method development and validation

    University essay from Örebro universitet/Institutionen för naturvetenskap och teknik

    Author : Mohammad Sadia; [2019]
    Keywords : ;

    Abstract : To comprise the future requirements to detect low levels of perfluoroalkane acids, includingbranched and linear perfluorooctane sulfonic acid (PFOS), perfluorooctanoic acid (PFOA),and perfluorohexane sulfonic acid (PFHxS) in food items, here analytical methods fordetermination of PFOS, PFOA and PFHxS in six different food matrices (cow milk, butter,chicken egg, chicken meat, beef, and fish) were optimized and validated. The optimizedmethod was based on alkaline digestion and solid-liquid extraction using acetonitrile,followed by solid phase extraction (SPE) using a weak anion exchange cartridge as clean-up. READ MORE