Essays about: "Time to Digital Converter TDC"

Showing result 1 - 5 of 9 essays containing the words Time to Digital Converter TDC.

  1. 1. A Digital Phase-Locked Loop for Frequency Synthesis using an Adaptive Pulse Shrinking TDC

    University essay from Lunds universitet/Institutionen för elektro- och informationsteknik

    Author : Viktor Lewin; [2023]
    Keywords : Phase-locked loop; PLL; DPLL; Frequency Synthesis; TDC; PFD; Technology and Engineering;

    Abstract : This thesis investigates a new type of Phase-Locked Loop (PLL) architecture which combines a phase/frequency detector (PFD) and a digital loop filter. The quantization is done by a time-to-digital converter which continuously shrinks the pulse coming from the PFD and registers how far it propagates. READ MORE

  2. 2. A digital integer-N PLL architecture using a pulse-shrinking TDC for mmWave applications.

    University essay from KTH/Skolan för elektroteknik och datavetenskap (EECS)

    Author : Simon Richter; [2023]
    Keywords : Phase-locked-loops; All-digital Phase-locked-loops; Time-to-digital converters; 5G and beyond; Radio-frequency design; Fas-låsd-loop; Helt-digital fas-låst-loop; Tid-till-digital-omvandlare; 5G och framtiden; Radio-frekvens design;

    Abstract : With the move of the broadband cellular network towards 5G taking off and the preparatory work on 6G and beyond starting, the need for low-complexity, low-power, and high-performance frequency synthesis using Phase-Locked Loop (PLL)s increases. As we get deeper into the mm-wave frequencies and push towards frequencies in the order of 50-70 GHz design challenges with existing PLL architectures, such as limited technology scaling and limited in-band noise performance become more apparent. READ MORE

  3. 3. A 1.8 ps Time-to-Digital Converter (TDC) Implemented in a 20 nm Field-Programmable Gate Array (FPGA) Using a Ones-Counter Encoding Scheme with Embedded Bin-Width Calibrations and Temperature Correction

    University essay from Linköpings universitet/Datorteknik

    Author : Engström Sven; [2020]
    Keywords : time-to-digital; time-to-digital converter; TDC; 1.8 ps; field-programmable gate array; FPGA; 20 nm; Xilinx; Kintex; UltraScale; tapped delay line; TDL; taps; carry-chain; ones-counter; bit-counter; bubbles; wave-union; embedded; temperature correction;

    Abstract : This thesis investigates the use of field-programmable gate arrays (FPGAs) to implement a time-to-digital converter (TDC) with on-chip calibration and temperature correction.Using carry-chains on the Xilinx Kintex UltraScale architecture to create a tapped delay line (TDL) has previously been proven to give good time resolution. READ MORE

  4. 4. Adaptive TDC : Implementation and Evaluation of an FPGA

    University essay from Linköpings universitet/Datorteknik

    Author : Simon Andersson Holmström; [2015]
    Keywords : TDC; Carry-chain; FPGA; Zynq; Delay;

    Abstract : Time to digital converter (TDC) is a digital unit that measures the time interval between two events.This is useful to determine the characteristics and patterns of a signal or an event. In this thesis ahybrid TDC is presented consisting of a tapped delay line and a clock counter principle. READ MORE

  5. 5. All-Digital ADC Design in 65 nm CMOS Technology

    University essay from Linköpings universitet/Elektroniksystem; Linköpings universitet/Tekniska högskolan

    Author : Srinivasa Rao Pathapati; [2014]
    Keywords : Digital ADC; TDC; VCO-based ADC; VCO-based quantizer;

    Abstract : The design of analog and complex mixed-signal circuits in a deep submicron CMOS process technology is a big challenge. This makes it desirable to shift data converter design towards the digital domain. READ MORE