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Showing result 1 - 5 of 9 essays matching the above criteria.

  1. 1. A Digital Design Flow - From Concept to RTL Description, Using Mathworks and Cadence's Tools

    University essay from Lunds universitet/Institutionen för elektro- och informationsteknik

    Author : Tor Hammarbäck; Jorge Deza Concori; [2022]
    Keywords : Technology and Engineering;

    Abstract : This report presents our digital design flow for creating high speed very large scale integration circuits using a fifth generation disruptive beamforming control and data processing circuit as example. The flow consists of different stages. READ MORE

  3. 2. Design space exploration using HLS in relation to code structuring

    University essay from KTH/Skolan för elektroteknik och datavetenskap (EECS)

    Author : Debraj Das; [2022]
    Keywords : Design Space Exploration DSE ; High level Synthesis HLS ; Design Methodology;

    Abstract : High Level Synthesis (HLS) is a methodology to translate a model developed in a high abstraction layer, e.g. C/C++/SystemC, that describes the algorithm into a Register-Transfer level (RTL) description like Verilog or VHDL. READ MORE

  4. 3. Evaluation of high-level synthesis tools for generation of Verilog code from MATLAB based environments

    University essay from Luleå tekniska universitet/Institutionen för system- och rymdteknik

    Author : Carl Bäck; [2020]
    Keywords : HLS; System Generator for DSP; Histogram; Xilinx Zynq UltraScale ; FPGA design workflow; Hardware Description Language Coder; HDL Coder; Field Programmable Gate Arrays; Image processing;

    Abstract : FPGAs are of interest in the signal processing domain as they provide the opportunity to run algorithms at very high speed. One possible use case is to sort incoming data in a measurement system, using e.g. a histogram method. READ MORE

  5. 4. Case study on Universal Verification Methodology(UVM) SystemC testbench for RTL verification

    University essay from Lunds universitet/Institutionen för elektro- och informationsteknik

    Author : Kevin Skaria Chacko; [2019]
    Keywords : Technology and Engineering;

    Abstract : This Master’s thesis aims to conduct a case study on using Universal Verification Methodology (UVM) in SystemC for Register-Transfer Level (RTL) verification. Verification of ASICs is very important nowadays especially in terms of production costs, time to market and the sustainability of products. READ MORE

  6. 5. Characterization of FPGA-based Arbiter Physical Unclonable Functions

    University essay from KTH/Skolan för elektroteknik och datavetenskap (EECS)

    Author : Jingnan Shao; [2019]
    Keywords : Arbiter PUF; FPGA; Altera; Verilog HDL; Arbiter PUF; FPGA; Altera; Verilog HDL;

    Abstract : The security of service, confidential data, and intellectual property are threatened by physical attacks, which usually include reading and tampering the data. In many cases, attackers can have access to the tools and equipment that can be used to read the memory or corrupt it, either by invasive or non-invasive means. READ MORE